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| P RE L I M I NA R Y LM3S101 Microcontroller DATA SHEET DS -LM3S 101- 00 C opyr ight (c) 2006 Lumi nary Micro , Inc. LM3S101 Data Sheet Legal Disclaimers and Trademark Information INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH LUMINARY MICRO PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN LUMINARY MICRO'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, LUMINARY MICRO ASSUMES NO LIABILITY WHATSOEVER, AND LUMINARY MICRO DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF LUMINARY MICRO'S PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. LUMINARY MICRO'S PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE-SUSTAINING APPLICATIONS. Luminary Micro may make changes to specifications and product descriptions at any time, without notice. Contact your local Luminary Micro sales office or your distributor to obtain the latest specifications before placing your product order. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Luminary Micro reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. Stellaris and the Luminary Micro logo are trademarks of Luminary Micro, Inc. or its subsidiaries in the United States and other countries. ARM and Thumb are registered trademarks, and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. Luminary Micro, Inc. 2499 South Capital of Texas Hwy, Suite A-100 Austin, TX 78746 Main: +1-512-279-8800 Fax: +1-512-279-8879 http://www.luminarymicro.com March 22, 2006 Preliminary 2 Table of Contents Legal Disclaimers and Trademark Information.............................................................................. 2 Revision History ............................................................................................................................. 12 About This Document..................................................................................................................... 13 Audience........................................................................................................................................................... 13 About This Manual............................................................................................................................................ 13 Related Documents .......................................................................................................................................... 13 Documentation Conventions............................................................................................................................. 13 1. 1.1 1.2 1.3 1.4 1.5 Architectural Overview............................................................................................................ 16 Product Features ...................................................................................................................................... 16 Target Applications ................................................................................................................................... 19 High-Level Block Diagram ........................................................................................................................ 20 Functional Overview ................................................................................................................................. 21 System Block Diagram.............................................................................................................................. 25 2. ARM Cortex-M3 Processor Core ............................................................................................ 26 2.1 Block Diagram........................................................................................................................................... 27 2.2 Functional Description .............................................................................................................................. 27 3. 4. 5. Memory Map ............................................................................................................................. 29 Interrupts .................................................................................................................................. 31 JTAG Interface ......................................................................................................................... 34 5.1 Block Diagram........................................................................................................................................... 35 5.2 Functional Description .............................................................................................................................. 35 5.3 Register Descriptions ................................................................................................................................ 39 6. System Control ........................................................................................................................ 44 6.1 Functional Description .............................................................................................................................. 44 6.2 Register Map............................................................................................................................................. 49 6.3 Register Descriptions ................................................................................................................................ 51 7. 7.1 7.2 7.3 7.4 7.5 Internal Memory ....................................................................................................................... 80 Block Diagram........................................................................................................................................... 80 Functional Description .............................................................................................................................. 80 Initialization and Configuration .................................................................................................................. 82 Register Map............................................................................................................................................. 83 Register Descriptions ................................................................................................................................ 83 8. 8.1 8.2 8.3 8.4 8.5 General-Purpose Input/Outputs (GPIOs)............................................................................... 93 Block Diagram........................................................................................................................................... 94 Functional Description .............................................................................................................................. 94 Initialization and Configuration .................................................................................................................. 97 Register Map............................................................................................................................................. 98 Register Descriptions ................................................................................................................................ 99 9. 9.1 9.2 9.3 9.4 9.5 General-Purpose Timers ....................................................................................................... 130 Block Diagram......................................................................................................................................... 131 Functional Description ............................................................................................................................ 131 Initialization and Configuration ................................................................................................................ 137 Register Map........................................................................................................................................... 140 Register Descriptions .............................................................................................................................. 140 3 Preliminary March 22, 2006 LM3S101 Data Sheet 10. Watchdog Timer..................................................................................................................... 160 10.1 Block Diagram......................................................................................................................................... 160 10.2 Functional Description ............................................................................................................................ 161 10.3 Initialization and Configuration ................................................................................................................ 161 10.4 Register Map........................................................................................................................................... 161 10.5 Register Descriptions .............................................................................................................................. 162 11. Universal Asynchronous Receiver/Transmitter (UART) .................................................... 182 11.1 Block Diagram......................................................................................................................................... 183 11.2 Functional Description ............................................................................................................................ 183 11.3 Initialization and Configuration ................................................................................................................ 186 11.4 Register Map........................................................................................................................................... 187 11.5 Register Descriptions .............................................................................................................................. 188 12. Synchronous Serial Interface (SSI)...................................................................................... 218 12.1 Block Diagram......................................................................................................................................... 218 12.2 Functional Description ............................................................................................................................ 219 12.3 Initialization and Configuration ................................................................................................................ 227 12.4 Register Map........................................................................................................................................... 228 12.5 Register Descriptions .............................................................................................................................. 228 13. Analog Comparators ............................................................................................................. 251 13.1 Block Diagram......................................................................................................................................... 251 13.2 Functional Description ............................................................................................................................ 251 13.3 Register Map........................................................................................................................................... 254 13.4 Register Descriptions .............................................................................................................................. 254 14. Pin Diagram............................................................................................................................ 262 15. Signal Tables.......................................................................................................................... 263 16. Operating Characteristics..................................................................................................... 270 17. Electrical Characteristics...................................................................................................... 271 17.1 DC Characteristics .................................................................................................................................. 271 17.2 AC Characteristics .................................................................................................................................. 273 18. Package Information ............................................................................................................. 282 Contact Information...................................................................................................................... 283 Ordering Information ....................................................................................................................................... 283 Development Kit ............................................................................................................................................. 283 March 22, 2006 Preliminary 4 List of Figures Figure 1-1. Figure 1-2. Figure 2-1. Figure 2-2. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 6-1. Figure 6-2. Figure 7-1. Figure 8-1. Figure 8-2. Figure 8-3. Figure 8-4. Figure 9-1. Figure 9-2. Figure 9-3. Figure 9-4. Figure 10-1. Figure 11-1. Figure 11-2. Figure 12-1. Figure 12-2. Figure 12-3. Figure 12-4. Figure 12-5. Figure 12-6. Figure 12-7. Figure 12-8. Figure 12-9. Figure 12-10. Figure 12-11. Figure 12-12. Figure 13-1. Figure 13-2. Figure 13-3. Figure 14-1. Figure 17-1. Figure 17-2. Figure 17-3. Figure 17-4. Figure 17-5. Figure 17-6. Stellaris High-Level Block Diagram ........................................................................................... 20 Stellaris System-Level Block Diagram....................................................................................... 25 CPU High-Level Block Diagram ............................................................................................... 27 TPIU Block Diagram .................................................................................................................. 28 JTAG Module Block Diagram .................................................................................................... 35 Test Access Port State Machine ............................................................................................... 38 IDCODE Register Format.......................................................................................................... 42 BYPASS Register Format ......................................................................................................... 42 Boundary Scan Register Format ............................................................................................... 43 External Circuitry to Extend Reset............................................................................................. 45 Main Clock Tree ........................................................................................................................ 48 Flash Block Diagram ................................................................................................................. 80 GPIO Module Block Diagram .................................................................................................... 94 GPIO Port Block Diagram.......................................................................................................... 95 GPIODATA Write Example........................................................................................................ 95 GPIODATA Read Example ....................................................................................................... 96 GPTM Block Diagram.............................................................................................................. 131 16-Bit Input Edge Count Mode Example ................................................................................. 135 16-Bit Input Edge Time Mode Example................................................................................... 136 16-Bit PWM Mode Example .................................................................................................... 137 Watchdog Timer Block Diagram.............................................................................................. 160 UART Block Diagram .............................................................................................................. 183 UART Character Frame........................................................................................................... 184 SSI Block Diagram .................................................................................................................. 218 TI Synchronous Serial Frame Format (Single Transfer).......................................................... 220 TI Synchronous Serial Frame Format (Continuous Transfer) ................................................. 221 Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................................... 222 Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................................. 222 Freescale SPI Frame Format with SPO=0 and SPH=1........................................................... 223 Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0............................... 223 Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0....................... 224 Freescale SPI Frame Format with SPO=1 and SPH=1........................................................... 224 National Semiconductor MICROWIRE Frame Format (Single Frame) ................................... 225 National Semiconductor MICROWIRE Frame Format (Continuous Transfers) ...................... 226 National Semiconductor MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements........................................................................................................... 227 Analog Comparator Block Diagram ......................................................................................... 251 Structure of Comparator Unit................................................................................................... 252 Comparator Internal Reference Structure ............................................................................... 253 Pin Connection Diagram.......................................................................................................... 262 SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement ................ 275 SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer................................. 276 SSI Timing for SPI Frame Format (FRF=00), with SPH=1...................................................... 276 JTAG Test Clock Input Timing................................................................................................. 277 JTAG Boundary Scan Timing .................................................................................................. 278 JTAG Test Access Port (TAP) Timing ..................................................................................... 278 5 Preliminary March 22, 2006 LM3S101 Data Sheet Figure 17-7. Figure 17-8. Figure 17-9. Figure 17-10. Figure 17-11. Figure 17-12. Figure 17-13. Figure 18-1. JTAG TRST Timing ................................................................................................................. 278 External Reset Timing (RST)................................................................................................... 280 Power-On Reset Timing .......................................................................................................... 280 Brown-Out Reset Timing ......................................................................................................... 280 Software Reset Timing ............................................................................................................ 281 Watchdog Reset Timing .......................................................................................................... 281 LDO Reset Timing ................................................................................................................... 281 28-Pin SOIC ............................................................................................................................ 282 March 22, 2006 Preliminary 6 List of Tables Table 0-1. Table 3-1. Table 4-1. Table 4-2. Table 5-1. Table 5-2. Table 6-1. Table 6-2. Table 6-3. Table 6-4. Table 7-1. Table 7-2. Table 8-1. Table 8-3. Table 8-2. Table 9-1. Table 9-2. Table 10-1. Table 11-1. Table 12-1. Table 13-1. Table 13-2. Table 13-3. Table 13-4. Table 15-1. Table 15-2. Table 15-3. Table 15-4. Table 16-1. Table 16-2. Table 17-1. Table 17-2. Table 17-3. Table 17-4. Table 17-5. Table 17-6. Table 17-7. Table 17-8. Table 17-9. Table 17-10. Table 17-11. Table 17-12. Documentation Conventions ..................................................................................................... 13 Memory Map.............................................................................................................................. 29 Exception Types ........................................................................................................................ 31 Interrupts ................................................................................................................................... 32 JTAG Port Pins Reset State ...................................................................................................... 36 JTAG Instruction Register Commands ...................................................................................... 40 System Control Register Map.................................................................................................... 49 VADJ to VOUT .......................................................................................................................... 61 Default Crystal Field Values and PLL Programming ................................................................. 72 PLL Mode Control...................................................................................................................... 73 Flash Protection Policy Combinations ....................................................................................... 81 Flash Register Map ................................................................................................................... 83 Pad Configuration Examples ..................................................................................................... 97 GPIO Register Map ................................................................................................................... 98 Interrupt Configuration Example................................................................................................ 98 16-Bit Timer With Prescaler Configurations ............................................................................ 133 GPTM Register Map................................................................................................................ 140 WDT Register Map .................................................................................................................. 161 UART Register Map ................................................................................................................ 187 SSI Register Map .................................................................................................................... 228 Comparator 0 Operating Modes .............................................................................................. 252 Comparator 1 Operating Modes .............................................................................................. 252 Internal Reference Voltage and ACREFCTL Field Values ...................................................... 253 Analog Comparator Register Map ........................................................................................... 254 Signals by Pin Number ............................................................................................................ 263 Signals by Signal Name .......................................................................................................... 265 Signals by Function, Except for GPIO ..................................................................................... 267 GPIO Pins and Alternate Functions......................................................................................... 268 Temperature Characteristics ................................................................................................... 270 Thermal Characteristics........................................................................................................... 270 Maximum Ratings.................................................................................................................... 271 Recommended DC Operating Conditions ............................................................................... 271 LDO Regulator Characteristics................................................................................................ 272 Power Specifications ............................................................................................................... 272 Power-Up and Brown-Out Detect Characteristics ................................................................... 273 Flash Memory Characteristics ................................................................................................. 273 Phase Locked Loop (PLL) Characteristics .............................................................................. 274 Clock Characteristics............................................................................................................... 274 SSI Characteristics .................................................................................................................. 275 JTAG Characteristics............................................................................................................... 277 GPIO Characteristics............................................................................................................... 279 Reset Characteristics .............................................................................................................. 279 7 Preliminary March 22, 2006 LM3S101 Data Sheet List of Registers System Control ............................................................................................................................... 44 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 1: Register 2: Register 3: Register 4: Register 5: Device Identification 0 (DID0), offset 0x000............................................................................ 52 Device Identification 1 (DID1), offset 0x004............................................................................ 53 Device Capabilities 0 (DC0), offset 0x008 .............................................................................. 55 Device Capabilities 1 (DC1), offset 0x010 .............................................................................. 56 Device Capabilities 2 (DC2), offset 0x014 .............................................................................. 57 Device Capabilities 3 (DC3), offset 0x018 .............................................................................. 58 Device Capabilities 4 (DC4), offset 0x01C.............................................................................. 59 Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030...................................... 60 LDO Power Control (LDOPCTL), offset 0x034 ....................................................................... 61 Software Reset Control 0 (SRCR0), offset 0x040................................................................... 62 Software Reset Control 1 (SRCR1), offset 0x044................................................................... 63 Software Reset Control 2 (SRCR2), offset 0x048................................................................... 64 Raw Interrupt Status (RIS), offset 0x050 ................................................................................ 65 Interrupt Mask Control (IMC), offset 0x054............................................................................. 66 Masked Interrupt Status and Clear (MISC), offset 0x058 ....................................................... 68 Reset Cause (RESC), offset 0x05C........................................................................................ 69 Run-Mode Clock Configuration (RCC), offset 0x060 .............................................................. 70 XTAL to PLL Translation (PLLCFG), offset 0x064.................................................................. 74 Run-Mode Clock Gating Control 0 (RCGC0), offset 0x100 .................................................... 75 Sleep-Mode Clock Gating Control 0 (SCGC0), offset 0x110 .................................................. 75 Deep-Sleep-Mode Clock Gating Control 0 (DCGC0), offset 0x120 ........................................ 75 Run-Mode Clock Gating Control 1 (RCGC1), offset 0x104 .................................................... 76 Sleep-Mode Clock Gating Control 1 (SCGC1), offset 0x114 .................................................. 76 Deep-Sleep-Mode Clock Gating Control 1 (DCGC1), offset 0x124 ........................................ 76 Run-Mode Clock Gating Control 2 (RCGC2), offset 0x108 .................................................... 77 Sleep-Mode Clock Gating Control 2 (SCGC2), offset 0x118 .................................................. 77 Deep-Sleep-Mode Clock Gating Control 2 (DCGC2), offset 0x128 ........................................ 77 Clock Verification Clear (CLKVCLR), offset 0x150 ................................................................. 78 Allow Unregulated LDO to Reset the Part (LDOARST), offset 0x160 .................................... 79 Flash Memory Protection Read Enable (FMPRE), offset 0x130............................................. 84 Flash Memory Protection Program Enable (FMPPE), offset 0x134........................................ 84 U Second Reload (USECRL), offset 0x140 ............................................................................ 85 Flash Memory Address (FMA), offset 0x000 .......................................................................... 86 Flash Memory Data (FMD), offset 0x004................................................................................ 87 Flash Memory Control (FMC), offset 0x008............................................................................ 88 Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ................................................ 90 Flash Controller Interrupt Mask (FCIM), offset 0x010............................................................. 91 Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ........................ 92 GPIO Data (GPIODATA), offset 0x000................................................................................. 100 GPIO Direction (GPIODIR), offset 0x400.............................................................................. 101 GPIO Interrupt Sense (GPIOIS), offset 0x404 ...................................................................... 102 GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................... 103 GPIO Interrupt Event (GPIOIEV), offset 0x40C .................................................................... 104 Internal Memory .............................................................................................................................. 80 General-Purpose Input/Outputs (GPIOs) ...................................................................................... 93 March 22, 2006 Preliminary 8 Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 1: Register 2: Register 3: GPIO Interrupt Mask (GPIOIM), offset 0x410 ....................................................................... 105 GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................... 106 GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ..................................................... 107 GPIO Interrupt Clear (GPIOICR), offset 0x41C .................................................................... 108 GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 .............................................. 109 GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................... 110 GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................... 111 GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................... 112 GPIO Open Drain Select (GPIOODR), offset 0x50C ............................................................ 113 GPIO Pull-Up Select (GPIOPUR), offset 0x510.................................................................... 114 GPIO Pull-Down Select (GPIOPDR), offset 0x514 ............................................................... 115 GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................... 116 GPIO Digital Input Enable (GPIODEN), offset 0x51C........................................................... 117 GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0......................................... 118 GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4......................................... 119 GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8......................................... 120 GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ........................................ 121 GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0......................................... 122 GPIO Peripheral Identification 1(GPIOPeriphID1), offset 0xFE4.......................................... 123 GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8......................................... 124 GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ........................................ 125 GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0............................................ 126 GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4............................................ 127 GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8............................................ 128 GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ........................................... 129 GPTM Configuration (GPTMCFG), offset 0x000 .................................................................. 141 GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................... 142 GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................... 143 GPTM Control (GPTMCTL), offset 0x00C ............................................................................ 144 GPTM Interrupt Mask (GPTMIMR), offset 0x018.................................................................. 146 GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C........................................................ 147 GPTM Masked Interrupt Status (GPTMMIS), offset 0x020................................................... 148 GPTM Interrupt Clear (GPTMICR), offset 0x024 .................................................................. 149 GPTM TimerA Interval Load (GPTMTAILR), offset 0x028.................................................... 150 GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................... 151 GPTM TimerA Match (GPTMTAMATCHR), offset 0x030..................................................... 152 GPTM TimerB Match (GPTMTBMATCHR), offset 0x034..................................................... 153 GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................... 154 GPTM TimerB Prescale (GPTMTBPR), offset 0x03C .......................................................... 155 GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ............................................. 156 GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ............................................. 157 GPTM TimerA (GPTMTAR), offset 0x048 ............................................................................ 158 GPTM TimerB (GPTMTBR), offset 0x04C............................................................................ 159 Watchdog Load (WDTLOAD), offset 0x000.......................................................................... 163 Watchdog Value (WDTVALUE), offset 0x004....................................................................... 164 Watchdog Control (WDTCTL), offset 0x008 ......................................................................... 165 General-Purpose Timers .............................................................................................................. 130 Watchdog Timer............................................................................................................................ 160 9 Preliminary March 22, 2006 LM3S101 Data Sheet Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Watchdog Interrupt Clear (WDTICR), offset 0x000 .............................................................. 166 Watchdog Raw Interrupt Status (WDTRIS), offset 0x010..................................................... 167 Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................... 168 Watchdog Lock (WDTLOCK), offset 0xC00.......................................................................... 169 Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 .................................. 170 Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 .................................. 171 Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 .................................. 172 Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC.................................. 173 Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 .................................. 174 Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 .................................. 175 Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 .................................. 176 Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC.................................. 177 Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 ..................................... 178 Watchdog PrimeCell Identification 1(WDTPCellID1), offset 0xFF4 ...................................... 179 Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 ..................................... 180 Watchdog PrimeCell Identification 3 (WDTPCellID0), offset 0xFFC..................................... 181 UART Data (UARTDR), offset 0x000.................................................................................... 189 UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004............................ 191 UART Flag (UARTFR), offset 0x018..................................................................................... 193 UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 .............................................. 195 UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028......................................... 196 UART Line Control (UARTLCRH), offset 0x02C................................................................... 197 UART Control (UARTCTL), offset 0x030 .............................................................................. 199 UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034.............................................. 200 UART Interrupt Mask (UARTIM), offset 0x038 ..................................................................... 201 UART Raw Interrupt Status (UARTRIS), offset 0x03C ......................................................... 203 UART Masked Interrupt Status (UARTMIS), offset 0x040.................................................... 204 UART Interrupt Clear (UARTICR), offset 0x044 ................................................................... 205 UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ....................................... 206 UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ....................................... 207 UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ....................................... 208 UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ...................................... 209 UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ....................................... 210 UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ....................................... 211 UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ....................................... 212 UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC....................................... 213 UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 .......................................... 214 UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 .......................................... 215 UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 .......................................... 216 UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ......................................... 217 SSI Control 0 (SSICR0), offset 0x000................................................................................... 229 SSI Control 1 (SSICR1), offset 0x004................................................................................... 231 SSI Data (SSIDR), offset 0x008............................................................................................ 232 SSI Status (SSISR), offset 0x00C......................................................................................... 233 SSI Clock Prescale (SSICPSR), offset 0x010 ...................................................................... 234 SSI Interrupt Mask (SSIIM), offset 0x014 ............................................................................. 235 Universal Asynchronous Receiver/Transmitter (UART) ........................................................... 182 Synchronous Serial Interface (SSI) ............................................................................................. 218 March 22, 2006 Preliminary 10 Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: SSI Raw Interrupt Status (SSIRIS), offset 0x018.................................................................. 236 SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................... 237 SSI Interrupt Clear (SSIICR), offset 0x020 ........................................................................... 238 SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................... 239 SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................... 240 SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................... 241 SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC .............................................. 242 SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................... 243 SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................... 244 SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................... 245 SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC............................................... 246 SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 .................................................. 247 SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 .................................................. 248 SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 .................................................. 249 SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ................................................. 250 Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 ..................................... 255 Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ........................................... 256 Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ............................................. 257 Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 258 Analog Comparator Status 0 (ACSTAT0), offset 0x20 ......................................................... 259 Analog Comparator Status 1 (ACSTAT1), offset 0x40 ......................................................... 259 Analog Comparator Control 0 (ACCTL0), offset 0x24 .......................................................... 260 Analog Comparator Control 1 (ACCTL1), offset 0x44 .......................................................... 260 Analog Comparators .................................................................................................................... 251 11 Preliminary March 22, 2006 LM3S101 Data Sheet Revision History This table provides a summary of the document revisions. Date March 2006 Revision 00 Description Initial public release. March 22, 2006 Preliminary 12 About This Document This data sheet provides reference information for the LM3S101 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM(R) CortexTM-M3 core. Audience This manual is intended for system software developers, hardware designers, and application developers. About This Manual This document is organized into sections that correspond to each major feature. Related Documents The following documents are referenced by the data sheet: ARM(R) CortexTM-M3 Technical Reference Manual CoreSightTM Design Kit Technical Reference Manual ARM(R) v7-M Architecture Application Level Reference Manual This documentation list was current as of publication date. Please check our web site at www.luminarymicro.com for additional related documentation, including application notes and white papers. Documentation Conventions This document uses the conventions shown in Table 0-1. Table 0-1. Documentation Conventions Notation General Register Notation REGISTER Registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more than one register. For example, SRCRn represents any (or all) of the three Software Reset Control registers: SRCR0, SRCR1, and SRCR2. A single bit in a register. Two or more consecutive and related bits. A hexadecimal increment to a register's address, relative to that module's base address as specified in Table 3-1, "Memory Map," on page 29. Registers are numbered consecutively throughout the document to aid in referencing them. The register number has no meaning to software. Meaning bit bit field offset 0xnnn Register N 13 Preliminary March 22, 2006 LM3S101 Data Sheet Table 0-1. Documentation Conventions Notation Meaning Register bits marked reserved are reserved for future use. Reserved bits return an indeterminate value, and should never be changed. Only write a reserved bit with its current value. The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in that register. This value in the register bit diagram indicates whether software running on the controller can change the value of the bit field. Software can read this field. Always write the chip reset value. Software can read or write this field. Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. This register type is primarily used for clearing interrupt status bits where the read operation provides the interrupt status and the write of the read value clears only the interrupts being reported at the time the register was read. reserved yy:xx Register Bit/Field Types RO R/W R/W1C W1C Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A read of the register returns no meaningful data. This register is typically used to clear the corresponding bit in an interrupt register. WO Only a write by software is valid; a read of the register returns no meaningful data. This value in the register bit diagram shows the bit/field value after any reset, unless noted. Bit cleared to 0 on chip reset. Bit set to 1 on chip reset. Nondeterministic. Register Bit/Field Reset Value 0 1 - Pin/Signal Notation [] pin signal assert a signal Pin alternate function; a pin defaults to the signal without the brackets. Refers to the physical connection on the package. Refers to the electrical signal encoding of a pin. Change the value of the signal from the logically False state to the logically True state. For active High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL below). March 22, 2006 Preliminary 14 Table 0-1. Documentation Conventions Notation Meaning Change the value of the signal from the logically True state to the logically False state. Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High. Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low. deassert a signal SIGNAL SIGNAL Numbers X An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and so on. Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF. Binary numbers are indicated with a b suffix, for example, 1011b. Decimal numbers are written without a prefix or suffix. 0x 15 Preliminary March 22, 2006 LM3S101 Data Sheet 1 Architectural Overview The Luminary Micro StellarisTM family of microcontrollers--the first ARM(R) CortexTM-M3 based controllers--brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. The LM3S101 controller in the Stellaris family offers the advantages of ARM's widely available development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community. Additionally, the controller uses ARM's Thumb(R)-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost. Luminary Micro offers a complete solution to get to market quickly, with a customer development board, white papers and application notes, and a strong support, sales, and distributor network. 1.1 Product Features The LM3S101 microcontroller includes the following product features: 32-Bit RISC Performance - 32-bit ARM(R) CortexTM-M3 v7M architecture optimized for small-footprint embedded applications - Thumb(R)-compatible Thumb-2-only instruction set processor core for high code density - 20-MHz operation - Hardware-division and single-cycle-multiplication - Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling - 14 interrupts with eight priority levels - Unaligned data access, enabling data to be efficiently packed into memory - Atomic bit manipulation (bit-banding) delivers maximum memory utilization and streamlined peripheral control Internal Memory - 8 KB single-cycle flash * * * User-managed flash block protection on a 2-KB block basis User-managed flash data programming User-defined and managed flash-protection block - 2 KB single-cycle SRAM General-Purpose Timers - Two timers, each of which can be configured as a single 32-bit timer or as two 16-bit timers - 32-bit Timer modes: * * * * Programmable one-shot timer Programmable periodic timer Real-Time Clock when using an external 32-KHz clock as the input User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU Halt flag during debug - 16-bit Timer modes: March 22, 2006 Preliminary 16 Architectural Overview * * * * * * * General-purpose timer function with an 8-bit prescaler Programmable one-shot timer Programmable periodic timer User-enabled stalling when the controller asserts CPU Halt flag during debug Input edge count capture Input edge time capture Simple PWM mode with software-programmable output inversion of the PWM signal - 16-bit Input Capture modes: - 16-bit PWM mode: ARM FiRM-compliant Watchdog Timer - 32-bit down counter with a programmable load register - Separate watchdog clock with an enable - Programmable interrupt generation logic with interrupt masking - Lock register protection from runaway software - Reset generation logic with an enable/disable - ARM PrimeCell(R)-compliant peripheral and cell identification registers - User-enabled stalling when the controller asserts the CPU Halt flag during debug Synchronous Serial Interface (SSI) - Master or slave operation - Programmable clock bit rate and prescale - Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep - Programmable interface operation for Freescale SPI, National Semiconductor MICROWIRETM, or Texas Instruments synchronous serial interfaces - Programmable data frame size from 4 to 16 bits - Internal loopback test mode for diagnostic/debug testing UART - Fully programmable 16C550-type UART - Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service loading - Programmable baud-rate generator with fractional divider - Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface - FIFO trigger levels of 1/8, 1/4, 1/2, 3/4 and 7/8 - Standard asynchronous communication bits for start, stop and parity - False start bit detection - Line-break generation and detection Analog Comparators - Two independent integrated analog comparators 17 Preliminary March 22, 2006 LM3S101 Data Sheet - Configurable for output to drive an output pin or generate an interrupt - Compare external pin input to external pin input or to internal programmable voltage reference GPIOs - 2 to 18 GPIOs, depending on configuration - Programmable interrupt generation as either edge-triggered or level-sensitive - Bit masking in both read and write operations through address lines - Programmable control for GPIO pad configuration: * * * * * Power - On-chip Linear Drop-Out (LDO) voltage regulator, with programmable output useradjustable from 2.25 V to 2.75 V - Low-power options on controller: Sleep and Deep-sleep modes - Low-power options for peripherals: software controls shutdown of individual peripherals - User-enabled LDO unregulated voltage detection and automatic reset - 3.3-V supply brownout detection and reporting via interrupt or reset Flexible Reset Sources - Power-on reset (POR) - Reset pin assertion - Brown-out (BOR) detector alerts to system power drops - Software reset - Watchdog timer reset - Internal linear drop-out (LDO) regulator output goes unregulated Additional Features - Six reset sources - Programmable clock source control - Clock gating to individual peripherals for power savings - IEEE 1149.1-1990 compliant Test Access Port (TAP) controller - Debug access via JTAG and Serial Wire interfaces - Full JTAG boundary scan Package - 28-pin RoHS-compliant SOIC - Commercial and industrial operating temperatures Weak pull-up or pull-down resistors 2-mA, 4-mA, and 8-mA pad drive Slew rate control for the 8-mA drive Open drain enables Digital input enables March 22, 2006 Preliminary 18 Architectural Overview 1.2 Target Applications Factory automation and control Industrial control power devices Building and home automation 19 Preliminary March 22, 2006 LM3S101 Data Sheet 1.3 High-Level Block Diagram Figure 1-1. Stellaris High-Level Block Diagram ARM Cortex-M3 (including Nested DCode bus Vectored Interrupt Controller (NVIC)) ICode bus Flash Memory Peripherals System Control & Clocks LMI JTAG Test Access Port (TAP) Controller APB Bridge SRAM General-Purpose Timers General-Purpose Input/Outputs (GPIOs) Watchdog Timer System Peripherals Universal Asynchronous Receiver/ Transmitter (UART) Peripheral Bus Synchronous Serial Interface (SSI) Serial Communications Peripherals Analog Comparators Analog Peripherals LM3S101 March 22, 2006 Preliminary 20 Architectural Overview 1.4 Functional Overview The following sections provide an overview of the features of the LM3S101 microcontroller. The chapter number in parenthesis indicates where that feature is discussed in detail. Ordering and support information can be found in "Contact Information" on page 506. 1.4.1 1.4.1.1 ARM CortexTM-M3 Processor Core (Section 2 on page 26) All members of the Stellaris product family, including the LM3S101 microcontroller, are designed around an ARM CortexTM-M3 processor core. The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Section 2, "ARM Cortex-M3 Processor Core," on page 26 provides an overview of the ARM core; the core is detailed in the ARM(R) CortexTM-M3 Technical Reference Manual. 1.4.1.2 Nested Vectored Interrupt Controller (NVIC) The LM3S101 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions are handled in Handler Mode. The processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Software can set eight priority levels on seven exceptions (system handlers) and 14 interrupts. Section 4, "Interrupts," on page 31 provides an overview of the NVIC controller and the interrupt map. Exceptions and interrupts are detailed in the ARM(R) CortexTM-M3 Technical Reference Manual. 1.4.2 Motor Control Peripherals To enhance motor control, the LM3S101 controller features Pulse Width Modulation (PWM) outputs. 1.4.2.1 PWM ("16-Bit PWM Mode" on page 139) Pulse Width Modulation (PWM) is a powerful technique often used to regulate a voltage by holding the frequency constant and varying the pulse width. On the LM3S101, PWM motion control functionality can be achieved through the motion control features of the general-purpose timers (using the CCP pins). The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable to support a simple PWM mode with a software-programmable output inversion of the PWM signal. 1.4.3 1.4.3.1 Analog Peripherals To handle analog signals, the LM3S101 controller offers two analog comparators. Analog Comparators (Section 13 on page 251) An analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result. 21 Preliminary March 22, 2006 LM3S101 Data Sheet The LM3S101 controller provides two independent integrated analog comparators that can be configured to drive an output or generate an interrupt. A comparator can compare a test voltage against any one of these voltages: An individual external reference voltage A shared single external reference voltage A shared internal reference voltage The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts to cause it to start capturing a sample sequence. The interrupt generation logic is separate. 1.4.4 Serial Communications Peripherals The LM3S101 controller supports both asynchronous and synchronous serial communications with one fully programmable 16C550-type UART and SSI serial communications. 1.4.4.1 UART (Section 11 on page 182) A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serialto-parallel converter), each clocked separately. The LM3S101 controller includes one fully programmable 16C550-type UART that supports data transfer speeds up to 460.8 Kbps. (Although similar in functionality to a 16C550 UART, it is not register compatible.) Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading. The UART can generate individually masked interrupts from the RX, TX, modem status, and error conditions. The module provides a single combined interrupt when any of the interrupts are asserted and are unmasked. 1.4.4.2 SSI (Section 12 on page 218) Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface. The LM3S101 controller SSI module provides the functionality for synchronous serial communications with peripheral devices, and can be configured to use the Freescale SPI, National Semiconductor MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also configurable, and can be set to be between 4 and 16 bits, inclusive. The SSI module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently. The SSI module can be configured as either a master or slave device. As a slave device, the SSI module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. The SSI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the SSI module's input clock. Bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral. The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a serial data line SDL and a serial clock line SCL). The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture. March 22, 2006 Preliminary 22 Architectural Overview The Stellaris I2C module provides the ability to communicate to other IC devices over an I2C bus. The I2C bus supports devices that can both transmit and receive (write and read) data. Devices on the I2C bus can be designated as either a master or a slave. The I2C module supports both sending and receiving data as either a master or a slave, and also supports the simultaneous operation as both a master and a slave. The four I2C modes are: Master Transmit, Master Receive, Slave Transmit, and Slave Receive. The Stellaris I2C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps). Both the I2C master and slave can generate interrupts. The I2C master generates interrupts when a transmit or receive operation completes (or aborts due to an error). The I2C slave generates interrupts when data has been sent or requested by a master. 1.4.5 1.4.5.1 System Peripherals Programmable GPIOs (Section 8 on page 93) General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The LM3S101 controller GPIO module is composed of three physical GPIO blocks, each corresponding to an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time Microcontrollers specification) and supports 2 to 18 programmable input/output pins. The number of GPIOs available depends on the peripherals being used (see Table 15-4 on page 268 for the signals available to each GPIO pin). The GPIO module features programmable interrupt generation as either edge-triggered or levelsensitive on all pins, programmable control for GPIO pad configuration, and bit masking in both read and write operations through address lines. 1.4.5.2 Two Programmable Timers (Section 9 on page 130) Programmable timers can be used to count or time external events that drive the Timer input pins. The LM3S101 controller General-Purpose Timer Module (GPTM) contains two GPTM blocks. Each GPTM block provides two 16-bit timer/counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32bit Real-Time Clock (RTC). When configured in 32-bit mode, a timer can run as a one-shot timer, periodic timer, or Real-Time Clock (RTC). When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event capture or Pulse Width Modulation (PWM) generation. 1.4.5.3 Watchdog Timer (Section 10 on page 160) A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. The LM3S101 controller Watchdog Timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, and a locking register. The Watchdog Timer can be configured to generate an interrupt to the controller on its first timeout, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. 1.4.6 Memory Peripherals The LM3S101 controller offers both SRAM and Flash memory. 23 Preliminary March 22, 2006 LM3S101 Data Sheet 1.4.6.1 SRAM (Section 7.2.1 on page 80) The LM3S101 static random access memory (SRAM) controller supports 2 KB SRAM. The internal SRAM of the Stellaris devices is located at address 0x20000000 of the device memory map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has introduced bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. 1.4.6.2 Flash (Section 7.2.2 on page 81) The LM3S101 Flash controller supports 8 KB of flash memory. The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually protected. The blocks can be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. 1.4.7 1.4.7.1 Additional Features Memory Map (Section 3 on page 29) A memory map lists the location of instructions and data in memory. The memory map for the LM3S101 controller can be found on page 29. Register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map. The ARM(R) CortexTM-M3 Technical Reference Manual provides further information on the memory map. 1.4.7.2 JTAG TAP Controller (Section 5 on page 34) The Joint Test Action Group (JTAG) port provides a standardized serial interface for controlling the Test Access Port (TAP) and associated test logic. The TAP, JTAG instruction register, and JTAG data registers can be used to test the interconnects of assembled printed circuit boards, obtain manufacturing information on the components, and observe and/or control the inputs and outputs of the controller during normal operation. The JTAG port provides a high degree of testability and chip-level access at a low cost. The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. The LMI JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while LMI JTAG instructions select the LMI TDO outputs. The multiplexer is controlled by the LMI JTAG controller, which has comprehensive programming for the ARM, LMI, and unimplemented JTAG instructions. 1.4.7.3 System Control and Clocks (Section 6 on page 44) System control determines the overall operation of the device. It provides information about the device, controls the clocking of the device and individual peripherals, and handles reset detection and reporting. March 22, 2006 Preliminary 24 Architectural Overview 1.4.8 Hardware Details Details on the pins and package can be found in the following sections: Section 14, "Pin Diagram," on page 262 Section 15, "Signal Tables," on page 263 Section 16, "Operating Characteristics," on page 270 Section 17, "Electrical Characteristics," on page 271 Section 18, "Package Information," on page 282 1.5 System Block Diagram Figure 1-2. VDD_3.3V LDO GND ARM Cortex-M3 (20 MHz) CM3Core NVIC Debug OSC0 OSC1 POR BOR System Control & Clocks GPIO Port A Watchdog Timer BOSC PLL APB Bridge SRAM (2 KB) Bus DCode ICode Flash (8 KB) LDO VDD_2.5V Stellaris System-Level Block Diagram RST Peripheral Bus GPIO Port B PB7/TRST Analog Comparators PB6/C0+ PB5/C0o/C1PB4/C0PB3 PB2 GP Timer1 PB1/32KHz PA5/SSITx PA4/SSIRx PA3/SSIFss PA2/SSIClk PA1/U0Tx PA0/U0Rx SSI UART0 GPIO Port C GP Timer0 PB0/CCP0 PC3/TDO/SWO PC2/TDI PC1/TMS/SWDIO PC0/TCK/SWCLK JTAG/SWD LM3S101 25 Preliminary March 22, 2006 LM3S101 Data Sheet 2 ARM Cortex-M3 Processor Core The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Features include: Compact core. Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications. Exceptional interrupt handling, by implementing the register manipulations required for handling an interrupt in hardware. Full-featured debug solution with a: - Serial Wire JTAG Debug Port (SWJ-DP) - Flash Patch and Breakpoint (FPB) unit for implementing breakpoints - Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources, and system profiling - Instrumentation Trace Macrocell (ITM) for support of printf style debugging - Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer The Stellaris family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, and building and home automation. For more information on the ARM Cortex-M3 processor core, see the ARM(R) CortexTM-M3 Technical Reference Manual. For information on SWJ-DP, see the CoreSightTM Design Kit Technical Reference Manual. March 22, 2006 Preliminary 26 ARM Cortex-M3 Processor Core 2.1 Block Diagram Figure 2-1. CPU High-Level Block Diagram Nested Vectored Interrupt Controller Interrupts Sleep Debug CM3 Core Instructions Data ARM Cortex-M3 Serial Wire Trace Trace Port Port (SWO) Interface Unit Private Peripheral Bus (external) ROM Table Flash Patch and Breakpoint Data Watchpoint and Trace Instrumentatio n Trace Macrocell Private Peripheral Bus (internal) Adv. HighPerf. Bus Access Port Bus Matrix Adv. Peripheral Bus I-code bus D-code bus System bus Serial Wire JTAG Debug Port 2.2 Functional Description Important: The ARM(R) CortexTM-M3 Technical Reference Manual describes all the features of an ARM Cortex-M3 in detail. However, these features differ based on the implementation. This section describes the Stellaris implementation. Luminary Micro has implemented the ARM Cortex-M3 core as shown in Figure 2-1. As noted in the ARM(R) CortexTM-M3 Technical Reference Manual, several Cortex-M3 components are flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the MPU, and the Nested Vectored Interrupt Controller (NVIC). 2.2.1 Serial Wire and JTAG Debug Luminary Micro has replaced the ARM SW-DP and JTAG-DP with the ARM CoreSightTMcompliant Serial Wire JTAG Debug Port (SWJ-DP) interface. This means Chapter 12, "Debug Port," of the ARM(R) CortexTM-M3 Technical Reference Manual does not apply to the Stellaris devices. The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the CoreSightTM Design Kit Technical Reference Manual for details on SWJ-DP. 27 Preliminary March 22, 2006 LM3S101 Data Sheet 2.2.2 Embedded Trace Macrocell (ETM) ETM was not implemented in the Stellaris devices. This means Chapters 15 and 16 of the ARM(R) CortexTM-M3 Technical Reference Manual can be ignored. 2.2.3 Trace Port Interface Unit (TPIU) The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace Port Analyzer. The Stellaris devices have implemented TPIU as shown in Figure 2-2. This is similar to the non-ETM version described in the ARM(R) CortexTM-M3 Technical Reference Manual, however, SWJ-DP only provides SWV output for the TPIU. Figure 2-2. TPIU Block Diagram Debug ATB Slave Port ATB Interface Asynchronous FIFO Trace Out (serializer) Serial Wire Trace Port (SWO) APB Slave Port APB Interface 2.2.4 ROM Table The default ROM table was implemented as described in the ARM(R) CortexTM-M3 Technical Reference Manual. 2.2.5 Memory Protection Unit (MPU) The LM3S101 controller does not include the memory protection unit (MPU) of the ARM CortexM3. 2.2.6 2.2.6.1 Nested Vectored Interrupt Controller (NVIC) Interrupts The ARM(R) CortexTM-M3 Technical Reference Manual describes the maximum number of interrupts and interrupt priorities. The Stellaris microcontrollers support 14 interrupts with eight priority levels. 2.2.6.2 SysTick Calibration Value Registers The SysTick Calibration Value register is not implemented. March 22, 2006 Preliminary 28 Memory Map 3 Memory Map The memory map for the LM3S101 is provided in Table 3-1. In this manual, register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map. See also Chapter 4, "Memory Map" in the ARM(R) CortexTM-M3 Technical Reference Manual. Table 3-1. Start Memory 0x00000000 0x20000000 0x20100000 0x22000000 0x24000000 Memory Map (Sheet 1 of 2) End Description For details on registers, see ... 0x1FFFFFFF 0x200FFFFF 0x21FFFFFF 0x23FFFFFF 0x3FFFFFFF On-chip flasha Bit-banded on-chip SRAMb Reserved non-bit banded SRAM spacec Bit-band alias of 0x20000000 through 0x200FFFFF Reserved non-bit-banded SRAM space page 83 - FiRM Peripherals 0x40000000 0x40001000 0x40004000 0x40005000 0x40006000 0x40007000 0x40008000 0x40009000 0x4000C000 0x4000D000 0x40010000 Peripherals 0x40020000 0x40024000 0x40028000 0x4002C000 0x40030000 0x40023FFF 0x40027FFF 0x4002BFFF 0x4002FFFF 0x40030FFF Reserved Reserved Reserved Reserved Timer0 page 140 0x40000FFF 0x40003FFF 0x40004FFF 0x40005FFF 0x40006FFF 0x40007FFF 0x40008FFF 0x4000BFFF 0x4000CFFF 0x4000FFFF 0x4001FFFF Watchdog timer Reserved for three additional watchdog timers (per FiRM specification) GPIO Port A GPIO Port B GPIO Port C Reserved for additional GPIO port (per FiRM specification) SSI Reserved for three additional SSIs (per FiRM specification) UART0 Reserved for additional UART (per FiRM specification) Reserved for future FiRM peripherals page 162 page 99 page 99 page 99 page 228 page 188 - 29 Preliminary March 22, 2006 LM3S101 Data Sheet Table 3-1. Start 0x40031000 0x40032000 0x40038000 0x4003C000 0x4003D000 0x400FD000 0x400FE000 0x40100000 0x42000000 0x44000000 Memory Map (Sheet 2 of 2) End 0x40031FFF 0x40037FFF 0x4003BFFF 0x4003CFFF 0x400FCFFF 0x400FDFFF 0x400FFFFF 0x41FFFFFF 0x43FFFFFF 0xDFFFFFFF Description Timer1 Reserved Reserved Analog comparators Reserved Flash control System control Reserved Bit-band alias of 0x40000000 through 0x400FFFFF Reserved For details on registers, see ... page 140 page 254 page 83 page 51 - Private Peripheral Bus 0xE0000000 0xE0001000 0xE0002000 0xE0003000 0xE000E000 0xE000F000 0xE0040000 0xE0041000 0xE0042000 0xE0100000 0xE0000FFF 0xE0001FFF 0xE0002FFF 0xE000DFFF 0xE000EFFF 0xE003FFFF 0xE0040FFF 0xE0041FFF 0xE00FFFFF 0xFFFFFFFF Instrumentation Trace Macrocell (ITM) Data Watchpoint and Trace (DWT) Flash Patch and Breakpoint (FPB) Reserved Nested Vectored Interrupt Controller (NVIC) Reserved Trace Port Interface Unit (TPIU) Reserved Reserved Reserved for vendor peripherals ARM(R) CortexTM-M3 Technical Reference Manual a. The available flash aliases throughout this address range. b. The available SRAM aliases throughout this address range. c. All reserved space returns random results when read and ignores writes. March 22, 2006 Preliminary 30 Interrupts 4 Interrupts The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. All exceptions are handled in Handler Mode. The processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor supports tail-chaining, which enables backto-back interrupts to be performed without the overhead of state saving and restoration. Table 4-1 lists all the exceptions. Software can set eight priority levels on seven of these exceptions (system handlers) as well as on 14 interrupts (listed in Table 4-2). Priorities on the system handlers are set with the NVIC System Handler Priority registers. Interrupts are enabled through the NVIC Interrupt Set Enable register and prioritized with the NVIC Interrupt Priority registers. You can also group priorities by splitting priority levels into pre-emption priorities and subpriorities. All the interrupt registers are described in Chapter 8, "Nested Vectored Interrupt Controller" in the ARM(R) CortexTM-M3 Technical Reference Manual. Internally, the highest user-settable priority (0) is treated as fourth priority, after a Reset, NMI, and a Hard Fault. Note that 0 is the default priority for all the settable priorities. If you assign the same priority level to two or more interrupts, their hardware priority (the lower the position number) determines the order in which the processor activates them. For example, if both GPIO Port A and GPIO Port B are priority level 1, then GPIO Port A has higher priority. See Chapter 5, "Exceptions" and Chapter 8, "Nested Vectored Interrupt Controller" in the ARM(R) CortexTM-M3 Technical Reference Manual for more information on exceptions and interrupts. Table 4-1. Exception Types Position 0 1 Prioritya -3 (highest) Description Stack top is loaded from first entry of vector table on reset. Invoked on power up and warm reset. On first instruction, drops to lowest priority (and then is called the base level of activation). This is asynchronous. Cannot be stopped or preempted by any exception but reset. This is asynchronous. An NMI is only producable by software, using the NVIC Interrupt Control State register. Hard Fault 3 -1 All classes of Fault, when the fault cannot activate due to priority or the configurable fault handler has been disabled. This is synchronous. MPU mismatch, including access violation and no match. This is synchronous. The priority of this exception can be changed. Bus Fault 5 settable Pre-fetch fault, memory access fault, and other address/memory related faults. This is synchronous when precise and asynchronous when imprecise. You can enable or disable this fault. Exception Type Reset Non-Maskable Interrupt 2 -2 Memory Management 4 settable 31 Preliminary March 22, 2006 LM3S101 Data Sheet Table 4-1. Exception Types Position 6 Prioritya settable Description Usage fault, such as undefined instruction executed or illegal state transition attempt. This is synchronous. Reserved System service call with SVC instruction. This is synchronous. Debug monitor (when not halting). This is synchronous, but only active when enabled. It does not activate if lower priority than the current activation. Reserved Pendable request for system service. This is asynchronous and only pended by software. System tick timer has fired. This is asynchronous. Asserted from outside the ARM Cortex-M3 core and fed through the NVIC (prioritized). These are all asynchronous. Table 4-2 lists the interrupts on the LM3S101 controller. Exception Type Usage Fault SVCall Debug Monitor 7-10 11 12 settable settable PendSV SysTick Interrupts 13 14 15 16 and above settable settable settable a. 0 is the default priority for all the settable priorities. Table 4-2. Interrupts Description GPIO Port A GPIO Port B GPIO Port C Reserved UART0 Reserved SSI Reserved Watchdog timer Timer0a Timer0b Timer1a Timer1b Interrupt (Bit in Interrupt Registers) 0 1 2 3-4 5 6 7 8-17 18 19 20 21 22 March 22, 2006 Preliminary 32 Interrupts Table 4-2. Interrupts Description Reserved Analog Comparator 0 Analog Comparator 1 Reserved System Control Flash Control Reserved Interrupt (Bit in Interrupt Registers) 23-24 25 26 27 28 29 30-31 33 Preliminary March 22, 2006 LM3S101 Data Sheet 5 JTAG Interface The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG Port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. The LMI JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while LMI JTAG instructions select the LMI TDO outputs. The multiplexer is controlled by the LMI JTAG controller, which has comprehensive programming for the ARM, LMI, and unimplemented JTAG instructions. The JTAG module has the following features: IEEE 1149.1-1990 compatible Test Access Port (TAP) controller Four-bit Instruction Register (IR) chain for storing JTAG instructions IEEE standard instructions: - BYPASS instruction - IDCODE instruction - SAMPLE/PRELOAD instruction - EXTEST instruction - INTEST instruction ARM additional instructions: - APACC instruction - DPACC instruction - ABORT instruction Integrated ARM Serial Wire Debug (SWD) See the ARM(R) CortexTM-M3 Technical Reference Manual for more information on the ARM JTAG controller. March 22, 2006 Preliminary 34 JTAG Interface 5.1 Figure 5-1. TRST TCK TMS Block Diagram JTAG Module Block Diagram TAP Controller TDI Instruction Register (IR) BYPASS Data Register Boundary Scan Data Register IDCODE Data Register ABORT Data Register DPACC Data Register APACC Data Register TDO Cortex-M3 Debug Port 5.2 Functional Description A high-level conceptual drawing of the JTAG module is shown in Figure 5-1. The JTAG module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel update registers. The TAP controller is a simple state machine controlled by the TRST, TCK and TMS inputs. The current state of the TAP controller depends on the current value of TRST and the sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel load registers. The current state of the TAP controller also determines whether the Instruction Register (IR) chain or one of the Data Register (DR) chains is being accessed. The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR) chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load register determines which DR chain is captured, shifted, or updated during the sequencing of the TAP controller. Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not capture, shift, or update any of the chains. Instructions that are not implemented decode to the BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see Table 5-2 for a list of implemented instructions). See "JTAG and Boundary Scan" on page 277 for JTAG timing diagrams. 35 Preliminary March 22, 2006 LM3S101 Data Sheet 5.2.1 JTAG Interface Pins The JTAG interface consists of five standard pins: TRST, TCK, TMS, TDI, and TDO. These pins and their associated reset state are given in Table 5-1. Detailed information on each pin follows. Table 5-1. Pin Name TRST TCK TMS TDI TDO JTAG Port Pins Reset State Data Direction Input Input Input Input Output Internal Pull-Up Enabled Enabled Enabled Enabled Enabled Internal Pull-Down Disabled Disabled Disabled Disabled Disabled Drive Strength N/A N/A N/A N/A 2-mA driver Drive Value N/A N/A N/A N/A High-Z 5.2.1.1 Test Reset Input (TRST) The TRST pin is an asynchronous active Low input signal for initializing and resetting the JTAG TAP controller and associated JTAG circuitry. When TRST is asserted, the TAP controller resets to the Test-Logic-Reset state and remains there while TRST is asserted. When the TAP controller enters the Test-Logic-Reset state, the Instruction Register (IR) resets to the default instruction, IDCODE. By default, the internal pull-up resistor on the TRST pin is enabled after reset. Changes to the pullup resistor settings on GPIO Port B should ensure that the internal pull-up resistor remains enabled on PB7/TRST; otherwise JTAG communication could be lost. 5.2.1.2 Test Clock Input (TCK) The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate independently of any other system clocks. In addition, it ensures that multiple JTAG TAP controllers that are daisy-chained together can synchronously communicate serial test data between components. During normal operation, TCK is driven by a free-running clock with a nominal 50% duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK is stopped at 0 or 1, the state of the TAP controller will not change and data in the JTAG instruction and data registers will not be lost. By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down resistors can be turned off to save internal power as long as the TCK pin is constantly being driven by an external source. 5.2.1.3 Test Mode Select (TMS) The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is entered. Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TMS to change on the falling edge of TCK. Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction, IDCODE. Therefore, this sequence can be used as a reset mechanism, similar to asserting TRST. The JTAG Test Access Port state machine can be seen in its entirety in Figure 5-2. March 22, 2006 Preliminary 36 JTAG Interface By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pullup resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC1/TMS; otherwise JTAG communication could be lost. 5.2.1.4 Test Data Input (TDI) The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is sampled on the rising edge of TCK and, depending on the current TAP state and the current instruction, presents this data to the proper shift register chain. Because the TDI pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pullup resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC2/TDI; otherwise JTAG communication could be lost. 5.2.1.5 Test Data Output (TDO) The TDO pin provides an output stream of serial information from the IR chain or the DR chains. The value of TDO depends on the current TAP state, the current instruction, and the data in the chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects the value on TDO to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDO pin is enabled after reset. This assures that the pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable during certain TAP controller states. 5.2.2 JTAG TAP Controller The JTAG TAP controller state machine is shown in Figure 5-2 on page 38. The TAP controller state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR) or the assertion of TRST. Asserting the correct sequence on the TMS pin allows the JTAG module to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed information on the function of the TAP controller and the operations that occur in each state, please refer to IEEE Standard 1149.1. 37 Preliminary March 22, 2006 LM3S101 Data Sheet Figure 5-2. Test Access Port State Machine Test Logic 1 0 Run Test Idle 0 1 Select DR Scan 0 1 Capture DR 0 Shift DR 1 Exit 1 DR 0 Pause DR 1 0 Exit 2 DR 1 Update DR 1 0 0 0 0 1 1 1 Select IR Scan 0 Capture IR 0 Shift IR 1 Exit 1 IR 0 Pause IR 1 Exit 2 IR 1 Update IR 1 0 0 0 1 1 5.2.3 Shift Registers The shift registers consist of a serial shift register chain and a parallel load register. The serial shift register chain samples specific information during the TAP controller's CAPTURE states and allows this information to be shifted out of TDO during the TAP controller's SHIFT states. While the sampled data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register on TDI. This new data is stored in the parallel load register during the TAP controller's UPDATE states. Each of the shift registers is discussed in detail in "Shift Registers" on page 38. 5.2.4 Operational Considerations There are certain operational considerations when using the JTAG module. Because the JTAG pins can be programmed to be GPIOs, board configuration and reset conditions on these pins must be considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the method for switching between these two operational modes requires clarification. March 22, 2006 Preliminary 38 JTAG Interface 5.2.4.1 GPIO Functionality Caution - If the JTAG pins will be used as GPIOs, it is possible to create a software sequence that prevents the debugger from connecting to the Stellaris microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger will not have enough time to connect and halt the controller before the JTAG pin functionality switches. This locks the debugger out of the part. This can be avoided with a software routine that restores JTAG functionality using an external trigger. When the controller is reset with either a POR or RST, the JTAG port pins default to their JTAG configurations. The default configuration includes enabling the pull-up resistors (setting GPIOPUR to 1 for PB7 and PC[3:0]) and enabling the alternate hardware function (setting GPIOAFSEL to 1 for PB7 and PC[3:0]) on the JTAG pins. It is possible for software to configure these pins as GPIOs after reset by writing 0s to the GPIOAFSEL registers of PB7 and PC[3:0]. If the user does not require the JTAG port for debugging or board-level testing, this will provide five more GPIOs for use in the design. Important: If the JTAG pins will be used as GPIOs in a design, PB7 and PC2 cannot have external pull-down resistors connected to both of them at the same time. If both pins are pulled Low during reset, the controller will have unpredictable behavior. If this happens, remove one or both of the pull-down resistors, and apply RST or powercycle the part. 5.2.4.2 ARM Serial Wire Debug (SWD) In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire debugger must be able to connect to the Cortex-M3 core without having to perform, or have any knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the SWD session begins. The preamble used to enable the SWD interface of the SWJ-DP module starts with the TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller through the following states: Run Test Idle, Select DR, Select IR, Capture IR, Exit1 IR, Update IR, Run Test Idle, Select DR, Select IR, Capture IR, Exit1 IR, Update IR, Run Test Idle, Select DR, Select IR, and Test-Logic-Reset states. Stepping through the JTAG TAP Instruction Register (IR) load sequences of the TAP state machine twice without shifting in a new instruction enables the SWD interface and disables the JTAG interface. For more information on this operation and the SWD interface, see the ARM(R) CortexTM-M3 Technical Reference Manual and the ARM(R) CoreSight Technical Reference Manual. Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG TAP controller is not fully compliant to the IEEE Standard 1149.1. This is the only instance where the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low probability of this sequence occuring during normal operation of the TAP controller, it should not affect normal performance of the JTAG interface. 5.3 Register Descriptions There are no APB-accessible registers in the JTAG TAP Controller or shift register chains. The registers within the JTAG controller are all accessed serially through the TAP Controller. The registers can be broken down into two main categories: Instruction Registers and Data Registers. 39 Preliminary March 22, 2006 LM3S101 Data Sheet 5.3.1 Instruction Register (IR) The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain with a parallel load register connected between the JTAG TDI and TDO pins. When the TAP Controller is placed in the correct states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the chain and updated, they are interpreted as the current instruction. The decode of the Instruction Register bits is shown in Table 5-2. A detailed explanation of each instruction, along with its associated Data Register, follows. Table 5-2. IR[3:0] 0000 0001 0010 1000 1010 1011 1110 1111 All Others JTAG Instruction Register Commands Instruction EXTEST INTEST SAMPLE / PRELOAD ABORT DPACC APACC IDCODE BYPASS Reserved Description Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction onto the pads. Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction into the controller. Captures the current I/O values and shifts the sampled values out of the Boundary Scan Chain while new preload data is shifted in. Shifts data into the ARM Debug Port Abort register. Shifts data into and out of the ARM DP Access register. Shifts data into and out of the ARM AC Access register. Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE chain and shifts it out. Connects TDI to TDO through a single shift register chain. Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO. 5.3.1.1 EXTEST Instruction The EXTEST instruction does not have an associated data register chain. The EXTEST instruction uses the data that has been preloaded into the Boundary Scan data register using the SAMPLE/ PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan data register associated with the outputs and output enables are used to drive the GPIO pads rather than the signals coming from the core. This allows tests to be developed that drive known values out of the controller, which can be used to verify connectivity. 5.3.1.2 INTEST Instruction The INTEST instruction does not have an associated data register chain. The INTEST instruction uses the data that has been preloaded into the Boundary Scan data register using the SAMPLE/ PRELOAD instruction. When the INTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan data register associated with the inputs are used to drive the signals going into the core rather than the signals coming from the GPIO pads. This allows tests to be developed that drive known values into the controller, which can be used for testing. It is important to note that although the RST input pin is on the Boundary Scan data register chain, it is only observable. March 22, 2006 Preliminary 40 JTAG Interface 5.3.1.3 SAMPLE/PRELOAD Instruction The SAMPLE/PRELOAD instruction connects the Boundary Scan data register chain between TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads new test data. Each GPIO pad has an associated input, output, and output enable signal. When the TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable signals to each of the GPIO pads is captured. These samples are serially shifted out of TDO while the TAP controller is in the Shift DR state and can be used for observation or comparison in various tests. While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary Scan data register, new data is being shifted into the Boundary Scan data register from TDI. Once the new data has been shifted into the Boundary Scan data register, the data is saved in the parallel load registers when the TAP controller enters the Update DR state. This update of the parallel load register preloads data into the Boundary Scan data register that is associated with each input, output, and output enable. This preloaded data can be used with the EXTEST and INTEST instructions to drive data into or out of the controller. Please see "Boundary Scan Data Register" on page 42 for more information. 5.3.1.4 ABORT Instruction The ABORT instruction connects the associated ABORT data register chain between TDI and TDO. This instruction provides read and write access to the ABORT register of the ARM Debug Access Port (DAP). Shifting the proper data into this data register clears various error bits or initiates a DAP abort of a previous request. Please see the "ABORT Data Register" on page 43 for more information. 5.3.1.5 DPACC Instruction The DPACC instruction connects the associated DPACC data register chain between TDI and TDO. This instruction provides read and write access to the DPACC register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to the ARM debug and status registers. Please see "DPACC Data Register" on page 43 for more information. 5.3.1.6 APACC Instruction The APACC instruction connects the associated APACC data register chain between TDI and TDO. This instruction provides read and write access to the APACC register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to internal components and buses through the Debug Port. Please see "APACC Data Register" on page 43 for more information. 5.3.1.7 IDCODE Instruction The IDCODE instruction connects the associated IDCODE data register chain between TDI and TDO. This instruction provides information on the manufacturer, part number, and version of the controller. This information can be used by testing equipment and debuggers to automatically configure their input and output data streams. IDCODE is the default instruction that is loaded into the JTAG Instruction Register when a power-on-reset (POR) is asserted, TRST is asserted, or the Test-Logic-Reset state is entered. Please see "IDCODE Data Register" on page 42 for more information. 5.3.1.8 BYPASS Instruction The BYPASS instruction connects the associated BYPASS data register chain between TDI and TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports. The BYPASS data register is a single-bit shift register. This instruction improves test 41 Preliminary March 22, 2006 LM3S101 Data Sheet efficiency by allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain by loading them with the BYPASS instruction. Please see "BYPASS Data Register" on page 42 for more information. 5.3.2 Data Registers The JTAG module contains six data registers. These include: IDCODE, BYPASS, Boundary Scan, APACC, DPACC, and ABORT serial data register chains. Each of these data registers is discussed in the following sections. 5.3.2.1 IDCODE Data Register The format for the 32-bit IDCODE data register defined by the IEEE Standard 1149.1 is shown in Figure 5-3. The standard requires that every JTAG-compliant device implement either the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE data register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB of 0. This allows auto configuration test tools to determine which instruction is the default instruction. The major uses of the JTAG port are for manufacturer testing of component assembly, and program development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE instruction outputs a value of 0x1BA00477. This value indicates an ARM Cortex-M3, Version 1 processor. This allows the debuggers to automatically configure themselves to work correctly with the Cortex-M3 during debug. Figure 5-3. 31 TDI IDCODE Register Format 28 27 Version Part Number 12 11 Manufacturer ID 10 1 TDO 5.3.2.2 BYPASS Data Register The format for the 1-bit BYPASS data register defined by the IEEE Standard 1149.1 is shown in Figure 5-4. The standard requires that every JTAG-compliant device implement either the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS data register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB of 1. This allows auto configuration test tools to determine which instruction is the default instruction. Figure 5-4. BYPASS Register Format 0 TDI 0 TDO 5.3.2.3 Boundary Scan Data Register The format of the Boundary Scan data register is show in Figure 5-5. Each GPIO pin, in a counterclockwise direction from the JTAG port pins, is included in the Boundary Scan data register. Each GPIO pin has three associated digital signals that are included in the chain. These signals are input, output, and output enable, and are arranged in that order as can be seen in the figure. In addition to the GPIO pins, the controller reset pin, RST, is included in the chain. Because the reset pin is always an input, only the input signal is included in the data register chain. March 22, 2006 Preliminary 42 JTAG Interface When the Boundary Scan data register is accessed with the SAMPLE/PRELOAD instruction, the input, output, and output enable from each digital pad are sampled and then shifted out of the chain to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with the EXTEST and INTEST instructions. These instructions either force data out of the controller, with the EXTEST instruction, or into the controller, with the INTEST instruction. Figure 5-5. TDI I N Boundary Scan Register Format O U T O E ... I N O U T O E I N I N O U T O E ... I N O U T O TDO E GPIO PB6 GPIO m RST GPIO m+1 GPIO n For detailed information on the order of the input, output, and output enable bits for each of the GPIO ports, please refer to the Stellaris Family Boundary Scan Description Language (BSDL) files, downloadable from the Luminary Micro website. 5.3.2.4 APACC Data Register The format for the 35-bit APACC data register defined by ARM is described in the ARM(R) CortexTM-M3 Technical Reference Manual. 5.3.2.5 DPACC Data Register The format for the 35-bit DPACC data register defined by ARM is described in the ARM(R) CortexTM-M3 Technical Reference Manual. 5.3.2.6 ABORT Data Register The format for the 35-bit ABORT data register defined by ARM is described in the ARM(R) CortexTM-M3 Technical Reference Manual. 43 Preliminary March 22, 2006 LM3S101 Data Sheet 6 System Control System control determines the overall operation of the device. It provides information about the device, controls the clocking of the device and individual peripherals, and handles reset detection and reporting. 6.1 Functional Description The System Control module provides the following capabilities: Device identification, see page 44 Local control, such as reset (see page 44), power (see page 47) and clock control (see page 47) System control (Run, Sleep, and Deep-Sleep modes), see page 49 6.1.1 Device Identification Seven read-only registers provide software with information on the microcontroller, such as version, part number, SRAM size, Flash size, and other features. See the DID0, DID1 and DC0DC4 registers starting on page 52. 6.1.2 Reset Control This section discusses aspects of hardware functions during reset as well as system software requirements following the reset sequence. 6.1.2.1 Reset Sources The controller has six sources of reset: 1. External reset input pin (RST) assertion, see page 44. 2. Power-on reset (POR), see page 45. 3. Internal brown-out (BOR) detector, see page 45. 4. Software-initiated reset (with the Software Reset registers), see page 46. 5. A watchdog timer reset condition violation, see page 46. 6. Internal linear drop-out (LDO) regulator output, see page 47. After a reset, the Reset Cause (RESC) register (see page 69) is set with the reset cause. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an external reset is the cause, and then all the other bits in the RESC register are cleared. Note: The main oscillator is used for external resets and power-on resets; the boot oscillator is used during the boot process by internal reset and clock verification circuitry. 6.1.2.2 RST Pin Assertion The external reset pin (RST) resets the controller. This resets the core and all the peripherals except the JTAG TAP controller (see "JTAG Interface" on page 34). The external reset sequence is as follows: 1. The external reset pin (RST) is asserted and then de-asserted. 2. After RST is de-assserted, the main crystal oscillator must be allowed to settle and there is an internal main oscillator counter that takes from 15-30 ms to account for this. During this time, internal reset to the rest of the controller is held active. March 22, 2006 Preliminary 44 System Control 3. The internal reset is released and the controller fetches and loads the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The external reset timing is shown in Figure 17-8 on page 280. 6.1.2.3 Power-On Reset (POR) The Power-On Reset (POR) circuitry detects a rise in power-supply voltage and generates an onchip reset pulse. To use the on-chip circuitry, the RST input needs a pull-up resistor (1K to 10K ohm). The device must be operating within the specified operating parameters at the point when the onchip power-on reset pulse is complete. The specified operating parameters include supply voltage, frequency, temperature, and so on. If the operating conditions are not met at the point of POR end, the Stellaris controller does not operate correctly. In this case, the reset must be extended using external circuitry. The RST input may be used with the circuit as shown in Figure 6-1. Figure 6-1. External Circuitry to Extend Reset Stellaris D1 R1 RST C1 R2 The R1 and C1 components define the power-on delay. The R2 resistor mitigates any leakage from the RST input. The diode discharges C1 rapidly when the power supply is turned off. The Power-On Reset sequence is as follows: 1. The controller waits for the later of external reset (RST) or internal POR to go inactive. 2. After the resets are inactive, the main crystal oscillator must be allowed to settle and there is an internal main oscillator counter that takes from 15-30 ms to account for this. During this time, internal reset to the rest of the controller is held active. 3. The internal reset is released and the controller fetches and loads the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The internal POR is only active on the initial power-up of the controller. The Power-On Reset timing is shown in Figure 17-9 on page 280. 6.1.2.4 Brown-Out Reset (BOR) A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used to reset the controller. This is initially disabled and may be enabled by software. The system provides a brown-out detection circuit that triggers if VDD drops below VBTH. The circuit is provided to guard against improper operation of logic and peripherals that operate off VDD and not the LDO voltage. If a brown-out condition is detected, the system may generate a controller interrupt or a system reset. The BOR circuit has a digital filter that protects against noiserelated detection. This feature may be optionally enabled. 45 Preliminary March 22, 2006 LM3S101 Data Sheet Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL) register (see page 60). The BORIOR bit in the PBORCTL register must be set for a brown-out to trigger a reset. The brown-out reset sequence is as follows: 1. When VDD drops below VBTH, an internal BOR condition is set. 2. If the BORWT bit in the PBORCTL register is set, the BOR condition is resampled sometime later (specified by BORTIM) to determine if the original condition was caused by noise. If the BOR condition is not met the second time, then no action is taken. 3. If the BOR condition exists, an internal reset is asserted. 4. The internal reset is released and the controller fetches and loads the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. 5. The internal BOR signal is released after 500 s to prevent another BOR condition from being set before software has a chance to investigate the original cause. The internal Brown-Out Reset timing is shown in Figure 17-10 on page 280. 6.1.2.5 Software Reset Each peripheral can be reset by software. There are three registers that control this function (see the SRCRn registers, starting on page 62). If the bit position corresponding to a peripheral is set, the peripheral is reset. The encoding of the reset registers is consistent with the encoding of the clock gating control for peripherals and on-chip functions (see "System Control" on page 49). Writing a bit lane with a value of 1 initiates a reset of the corresponding unit. Note that all reset signals for all clocks of the specified unit are asserted as a result of a software-initiated reset. The entire system can be reset by software also. Setting the SYSRESETREQ bit in the Cortex-M3 Application Interrupt and Reset Control register resets the entire system including the core. The software-initiated system reset sequence is as follows: 1. A software system reset in initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3 Application Interrupt and Reset Control register. 2. An internal reset is asserted. 3. The internal reset is released and the controller fetches and loads the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The software-initiated system reset timing is shown in Figure 17-11 on page 281. 6.1.2.6 Watchdog Timer Reset The watchdog timer module's function is to prevent system hangs. The watchdog timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer Load (WDTLOAD) register (see page 163), and the timer resumes counting down from that value. If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset sequence is as follows: 1. The watchdog timer times out for the second time without being serviced. 2. An internal reset is asserted. March 22, 2006 Preliminary 46 System Control 3. The internal reset is released and the controller fetches and loads the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The watchdog reset timing is shown in Figure 17-12 on page 281. 6.1.2.7 Linear Drop-Out A reset can be made when the internal linear drop-out (LDO) regulator output goes unregulated. This is initially disabled and may be enabled by software. LDO is controlled with the LDO Power Control (LDOPCTL) register (see page 61). The LDO reset sequence is as follows: 1. LDO goes unregulated and the LDOARST bit in the LDOARST register is set. 2. An internal reset is asserted. 3. The internal reset is released and the controller fetches and loads the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The LDO reset timing is shown in Figure 17-13 on page 281. 6.1.3 Power Control The LDO regulator permits the adjustment of the on-chip output voltage (VOUT). The output may be adjusted in 50 mV increments between the range of 2.25 V through 2.75 V. The adjustment is made through the VADJ field of the LDO Power Control (LDOPCTL) register (see page 61). 6.1.4 6.1.4.1 Clock Control System control determines the clocking and control of clocks in this part. Fundamental Clock Sources There are two fundamental clock sources for use in the device: The main oscillator, driven from either an external crystal or a single-ended source. As a crystal, the main oscillator source is specified to run from 1-8 MHz. However, when the crystal is being used as the PLL source, it must be from 5-8 MHz to meet PLL requirements. As a single-ended source, the range is from DC to the specified speed of the device. The boot oscillator, which is an on-chip free running clock. The boot oscillator is specified to run at 15 MHz 30%. It can be used to clock the system but the tolerance of frequency range must be met. The internal system clock may be driven by either of the above two reference sources as well as the internal PLL, provided that the PLL input is connected to a clock source that meets its AC requirements. Nearly all of the control for the clocks is provided by the Run-Mode Clock Configuration (RCC) register (see page 70). Figure 6-2 shows the logic for the main clock tree. The peripheral blocks are driven by the System Clock signal and can be programmatically enabled/disabled. 47 Preliminary March 22, 2006 LM3S101 Data Sheet Figure 6-2. Main Clock Tree USESYSa OSC1 OSC2 Main Osc 1-8 MHz SYSDIVa Boot Osc 15 MHz PLL /4 OSCSRC a System Clock (200MHz output ) OEN a a BYPASS a XTAL PWRDNa a. These are bit fields within the Run-Mode Clock Configuration (RCC) register 6.1.4.2 PLL Frequency Configuration The user does not have direct control over the PLL frequency, but is required to match the external crystal used to an internal PLL-Crystal table. This table is used to create the best fit for PLL parameters to the crystal chosen. Not all crystals result in the PLL operating at exactly 200 MHz, though the frequency will be within 1%; non-exact values are fine, if tolerated by the system. The result of the lookup is kept in the XTAL to PLL Translation (PLLCTL) register (see page 74). Table 6-3 on page 72 describes the available crystal choices and default programming of the PLLCTL register. The crystal number is written into the XTAL field of the Run-Mode Clock Configuration (RCC) register (see page 70). Any time the XTAL field changes, a read of the internal table is performed to get the correct value. Table 6-3 on page 72 describes the available crystal choices and default programming values. 6.1.4.3 PLL Modes The PLL has two modes of operation: Normal and Power-Down Normal: The PLL multiplies the input clock reference and drives the output. Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output. The modes are programmed using the Run-Mode Clock Configuration (RCC) register fields as shown in Table 6-4 on page 73. 6.1.4.4 PLL Operation If the PLL configuration is changed, the PLL output is not stable for a period of time (PLL TREADY=0.5 ms) and during this time, the PLL is not usable as a clock reference. The PLL is changed by one of the following: Change to the XTAL value in the Run-Mode Clock Configuration (RCC) register (see page 70)--writes of the same value will not cause a relock). Change in the PLL from Power-Down to Normal mode. A counter is defined to measure the TREADY requirement. The counter is clocked by the boot oscillator. The range of the boot oscillator has been taken into account and the down counter is set to 0x3000 (that is, ~800 us at a 15-MHz boot oscillator clock). Hardware is provided to keep the PLL from being used as a system clock until the TREADY condition is met after one of the two March 22, 2006 Preliminary 48 System Control changes above. It is the user's responsibility to have a stable clock source (like the main oscillator) before the RCC register is switched to use the PLL. 6.1.4.5 Clock Verification Timers There are three identical clock verification circuits that can be enabled though software. The circuit checks the faster clock by a slower clock using timers: The main oscillator checks the PLL. The main oscillator checks the boot oscillator. The boot oscillator divided by 64 checks the main oscillator. If the verification timer function is enabled and a failure is detected, the main clock tree is immediately switched to a working clock and an interrupt is generated to the controller. Software can then determine the course of action to take. The actual failure indication and clock switching does not clear without a write to the CLKVCLR register, an external reset, or a POR reset. The clock verification timers are controlled by the PLLVER, BOSCVER, and MOSCVER bits in the RCC register (see page 70). 6.1.5 System Control For power-savings purposes, the RCGCn, SCGCn, and DCGCn registers control the clock gating logic for each peripheral or block in the system while the controller is in Run, Sleep, and DeepSleep mode, respectively. The DC1, DC2 and DC4 registers act as a write mask for the RCGCn, SCGCn, and DCGCn registers. In Run mode, the controller is actively executing code. In Sleep mode, the clocking of the device is unchanged but the controller no longer executes code (and is no longer clocked). In Deep-Sleep mode, the clocking of the device may change (depending on the Run mode clock configuration) and the controller no longer executes code (and is no longer clocked). An interrupt returns the device to Run mode from one of the sleep modes; the sleep modes are entered on request from the code. 6.2 Register Map Table 6-1 lists the System Control registers, grouped by function. All addresses given are relative to the System Control base address of 0x400FE000. Table 6-1. Offset System Control Register Map (Sheet 1 of 2) Name Reset Type Description See page Device Identification and Capabilities 0x000 0x004 0x008 0x010 0x014 DID0 DID1 DC0 DC1 DC2 0x70003 0x901F 0x3030011 RO RO RO RO RO Device identification 0 Device identification 1 Device capabilities 0 Device capabilities 1 Device capabilities 2 52 53 55 56 57 49 Preliminary March 22, 2006 LM3S101 Data Sheet Table 6-1. Offset 0x018 0x01C System Control Register Map (Sheet 2 of 2) Name DC3 DC4 Reset 0x810003C0 0x7 Type RO RO Description Device Capabilities 3 Device Capabilities 4 See page 58 59 Local Control 0x030 0x034 0x040 0x044 0x048 0x050 0x054 0x058 0x05C 0x060 0x064 PBORCTL LDOPCTL SRCR0 SRCR1 SRCR2 RIS IMC MISC RESC RCC PLLCFG 0x00007FFD 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x7803AC0 R/W R/W R/W R/W R/W RO R/W R/W1C R/W R/W RO Power-On and Brown-Out Reset Control LDO Power Control Software Reset Control 0 Software Reset Control 1 Software Reset Control 2 Raw Interrupt Status Interrupt Mask Control Masked Interrupt Status and Clear Reset Cause Run-Mode Clock Configuration XTAL to PLL translation 60 61 62 63 64 65 66 68 69 70 74 System Control 0x100 0x104 0x108 0x110 0x114 0x118 0x120 0x124 0x128 0x150 0x160 RCGC0 RCGC1 RCGC2 SCGC0 SCGC1 SCGC2 DCGC0 DCGC1 DCGC2 CLKVCLR LDOARST 0x00000001 0x00000000 0x00000000 0x00000001 0x00000000 0x00000000 0x00000001 0x00000000 0x00000000 0x00000000 0x00000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Run-Mode Clock Gating Control 0 Run-Mode Clock Gating Control 1 Run-Mode Clock Gating Control 2 Sleep-Mode Clock Gating Control 0 Sleep-Mode Clock Gating Control 1 Sleep-Mode Clock Gating Control 2 Deep-Sleep-Mode Clock Gating Control 0 Deep-Sleep-Mode Clock Gating Control 1 Deep-Sleep-Mode Clock Gating Control 2 Clock verification clear Allow unregulated LDO to reset the part 75 76 77 75 76 77 75 76 77 78 79 March 22, 2006 Preliminary 50 System Control 6.3 Register Descriptions The remainder of this section lists and describes the System Control registers, in numerical order by address offset. 51 Preliminary March 22, 2006 LM3S101 Data Sheet Register 1: Device Identification 0 (DID0), offset 0x000 This register identifies the version of the device. Device Identification 0 (DID0) Offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 VER RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 reserved RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 MAJOR Type Reset RO RO RO RO RO RO RO RO RO RO RO RO - MINOR RO RO RO RO - Bit/Field 31 30:28 Name reserved VER Type RO RO Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. This field defines the version of the DID0 register format: 0=Register version for the Stellaris microcontrollers 27:16 15:8 reserved MAJOR RO RO 0 - Reserved bits return an indeterminate value, and should never be changed. This field specifies the major revision number of the device. The major revision number is indicated in the part number as a letter (A for first revision, B for second, and so on). This field is encoded as follows: 0: Revision A (initial device) 1: Revision B (first revision) and so on. 7:0 MINOR RO - This field specifies the minor revision number of the device. This field is numeric and is encoded as follows: 0: No changes. Major revision was most recent update. 1: One interconnect change made since last major revision update. 2: Two interconnect changes made since last major revision update. and so on. March 22, 2006 Preliminary 52 System Control Register 2: Device Identification 1 (DID1), offset 0x004 This register identifies the device family, part number, temperature range, and package type. Device Identification 1 (DID1) Offset 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VER Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 FAM RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 PARTNO RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO - TEMP RO RO RO 0 PKG RO 0 RoHS RO 1 RO - QUAL RO - Bit/Field 31:28 Name VER Type RO Reset 0x00 Description This field defines the version of the DID1 register format: 0=Register version for the Stellaris microcontrollers 27:24 FAM RO 0x00 Family This field provides the family identification of the device within the Luminary Micro product portfolio. The 0x00 value indicates the Stellaris family of microcontrollers. 23:16 PARTNO RO 0x01 Part Number This field provides the part number of the device within the family. The 0x01 value indicates the LM3S101 microcontroller. 15:8 7:5 reserved TEMP RO RO 0 see table Reserved bits return an indeterminate value, and should never be changed. Temperature Range This field specifies the temperature rating of the device. This field is encoded as follows: TEMP 000 001 010-111 Description Commercial temperature range (0C to 70C) Industrial temperature range (-40C to 85C) Reserved 4:3 2 PKG RoHS RO RO 0x0 1 This field specifies the package type, where 0 indicates a 28-pin SOIC package. RoHS-Compliance The 1 specifies the device is RoHS-compliant. 53 Preliminary March 22, 2006 LM3S101 Data Sheet Bit/Field 1:0 Name QUAL Type RO Reset see table Description This field specifies the qualification status of the device. This field is encoded as follows: QUAL 00 01 10 11 Description Engineering Sample (unqualified) Pilot Production (unqualified) Fully Qualified Reserved March 22, 2006 Preliminary 54 System Control Register 3: Device Capabilities 0 (DC0), offset 0x008 This register is predefined by the part and can be used to verify features. Device Capabilities Register 0 (DC0) Offset 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRAMSZ Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 1 2 RO 1 1 RO 1 0 FLSHSZ Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 Bit/Field 31:16 15:0 Name SRAMSZ FLSHSZ Type RO RO Reset 0x07 0x03 Description Indicates the size of the on-chip SRAM. The value of 0x07 indicates 2 KB of SRAM. Indicates the size of the on-chip flash memory. The value of 0x03 indicates 8 KB of Flash. 55 Preliminary March 22, 2006 LM3S101 Data Sheet Register 4: Device Capabilities 1 (DC1), offset 0x010 This register is predefined by the part and can be used to verify features. It also acts as a mask for write operations to the Run-Mode Clock Gating Control 0 (RCGC0) register (see page 75), Sleep-Mode Clock Gating Control 0 (SCGC0) register (see page 75), and Deep-Sleep-Mode Clock Gating Control 0 (DCGC0) register (see page 75). Device Capabilities 1 (DC1) Offset 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 MINSYSDIV Type Reset RO 1 RO 0 RO 0 RO 1 RO 0 reserved RO 0 RO 0 RO 0 MPU RO 0 reserved RO 0 RO 0 PLL RO 1 WDT RO 1 SWO RO 1 SWD RO 1 JTAG RO 1 Bit/Field 31:16 15:12 11:8 7 Name reserved MINSYSDIV reserved MPU Type RO RO RO RO Reset 0 0x09 0 0x0 Description Reserved bits return an indeterminate value, and should never be changed. The reset value is hardware-dependent. The value of 0x09 specifies a 20-MHz CPU clock with a PLL divider of 10. Reserved bits return an indeterminate value, and should never be changed. This bit indicates whether the Memory Protection Unit (MPU) in the Cortex-M3 is available. A 0 indicates the MPU is not available; a 1 indicates the MPU is available. See the ARM(R) CortexTM-M3 Technical Reference Manual for details on the MPU. 6:5 4 3 2 1 0 reserved PLL WDTa SWOa SWDa JTAGa RO RO RO RO RO RO 0 1 1 1 1 1 Reserved bits return an indeterminate value, and should never be changed. A 1 in this field indicates the presence of an implemented PLL in the device. A 1 in this field indicates a watchdog timer on the device. A 1 in this field indicates the presence of the ARM Serial Wire Output (SWO) trace port capabilities. A 1 in this field indicates the presence of the ARM Serial Wire Debug (SWD) capabilities. A 1 in this field indicates the presence of a JTAG port. a. These bits mask the Run-Mode Clock Gating Control 0 (RCGC0) register (see page 113), Sleep-Mode Clock Gating Control 0 (SCGC0) register (see page 113), and Deep-Sleep-Mode Clock Gating Control 0 (DCGC0) register (see page 113). Bits that are not noted are passed as 0. ADCSP is clipped to the maximum value specified in DC1. March 22, 2006 Preliminary 56 System Control Register 5: Device Capabilities 2 (DC2), offset 0x014 This register is predefined by the part and can be used to verify features. It also acts as a mask for write operations to the Run-Mode Clock Gating Control 1 (RCGC1) register (see page 76), Sleep-Mode Clock Gating Control 1 (SCGC1) register (see page 76), and Deep-Sleep-Mode Clock Gating Control 1 (DCGC1) register (see page 76). Device Capabilities 2 (DC2) Offset 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 COMP1 COMP0 RO 1 9 RO 1 8 RO 0 7 RO 0 6 reserved RO 0 5 RO 0 4 RO 0 3 RO 0 2 GPTM1 GPTM0 RO 1 1 RO 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 SSI RO 1 RO 0 reserved RO 0 RO 0 UART0 RO 1 Bit/Field 31:26 25 24 23:18 17 16 15:5 4 3:1 0 Name reserved COMP1 COMP0 reserved GPTM1 GPTM0 reserved SSI reserved UART0 Type RO RO RO RO RO RO RO RO RO RO Reset 0 1 1 0 1 1 0 1 0 1 Description Reserved bits return an indeterminate value, and should never be changed. A 1 in this field indicates the presence of analog comparator 1. A 1 in this field indicates the presence of analog comparator 0. Reserved bits return an indeterminate value, and should never be changed. A 1 in this field indicates the presence of General-Purpose Timer module 1. A 1 in this field indicates the presence of General-Purpose Timer module 0. Reserved bits return an indeterminate value, and should never be changed. A 1 in this field indicates the presence of the SSI module. Reserved bits return an indeterminate value, and should never be changed. A 1 in this field indicates the presence of the UART0 module. 57 Preliminary March 22, 2006 LM3S101 Data Sheet Register 6: Device Capabilities 3 (DC3), offset 0x018 This register is predefined by the part and can be used to verify features. Device Capabilities 3 (DC3) Offset 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 32KHz Type Reset RO 1 15 RO 0 14 RO 0 13 reserved RO 0 12 RO 0 11 RO 0 10 RO 0 9 CCP0 RO 1 8 RO 0 7 RO 0 6 RO 0 5 reserved RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 C1RO 1 C0o RO 1 C0+ RO 1 C0RO 1 RO 0 RO 0 reserved RO 0 RO 0 RO 0 RO 0 Bit/Field 31 30:25 24 23:10 9 8 7 6 5:0 Name 32KHz reserved CCP0 reserved C1C0o C0+ C0reserved Type RO RO RO RO RO RO RO RO RO Reset 1 0 1 0 1 1 1 1 0 Description A 1 in this field indicates the presence of a 32-KHz input pin. Reserved bits return an indeterminate value, and should never be changed. A 1 in this field indicates the presence of the Capture/ Compare/PWM pin 0. Reserved bits return an indeterminate value, and should never be changed. A 1 in this field indicates the presence of the C1- pin. A 1 in this field indicates the presence of the C0o pin. A 1 in this field indicates the presence of the C0+ pin. A 1 in this field indicates the presence of the C0- pin. Reserved bits return an indeterminate value, and should never be changed. March 22, 2006 Preliminary 58 System Control Register 7: Device Capabilities 4 (DC4), offset 0x01C This register is predefined by the part and can be used to verify features. It also acts as a mask for write operations to the Run-Mode Clock Gating Control 2 (RCGC2) register (see page 77), Sleep-Mode Clock Gating Control 2 (SCGC2) register (see page 77), and Deep-Sleep-Mode Clock Gating Control 2 (DCGC2) register (see page 77). Device Capabilities 4 (DC4) Offset 0x01C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PORTC PORTB PORTA RO 1 RO 1 RO 1 Bit/Field 31:3 2 1 0 Name reserved PORTC PORTB PORTA Type RO RO RO RO Reset 0 1 1 1 Description Reserved bits return an indeterminate value, and should never be changed. A 1 in this field indicates the presence of GPIO Port C. A 1 in this field indicates the presence of GPIO Port B. A 1 in this field indicates the presence of GPIO Port A. 59 Preliminary March 22, 2006 LM3S101 Data Sheet Register 8: Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030 This register is responsible for controlling reset conditions after initial power-on reset. Power-On and Brown-Out Reset Control (PBORCTL) Offset 0x030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 BORTIM Type Reset R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 BORIOR BORWT R/W 0 R/W 1 Bit/Field 31:16 15:2 Name reserved BORTIM Type RO R/W Reset 0 0x1FFF Description Reserved bits return an indeterminate value, and should never be changed. This field specifies the number of boot oscillator clocks delayed before the BOR output is resampled if the BORWT bit is set. The width of this field is derived by the tBOR width of 500 s and the boot oscillator (BOSC) frequency of 15 MHz 30%. At +30%, the counter value has to exceed 10,000. 1 BORIOR R/W 0 BOR Interrupt or Reset This bit controls how a BOR event is signaled to the controller. If set, a reset is signaled. Otherwise, an interrupt is signaled. 0 BORWT R/W 1 BOR Wait and Check for Noise This field specifies the response to a brown-out signal assertion. If BORWT is set to 1, the controller waits BORTIM BOSC periods before resampling the BOR output, and if asserted, it signals a BOR condition interrupt or reset. If the BOR resample is deasserted, the cause of the initial assertion was likely noise and the interrupt or reset is suppressed. If BORWT is 0, BOR assertions do not resample the output and any condition is reported immediately if enabled. March 22, 2006 Preliminary 60 System Control Register 9: LDO Power Control (LDOPCTL), offset 0x034 The VADJ field in this register adjusts the on-chip output voltage (VOUT). LDO Power Control (LDOPCTL) Offset 0x034 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 VADJ R/W 0 R/W 0 R/W 0 Bit/Field 31:6 5:0 Name reserved VADJ Type RO R/W Reset 0 0x0 Description Reserved bits return an indeterminate value, and should never be changed. This field specifies the value applied to the SEL_VOUT[5:0] LDO input. The programming values for the VADJ field are provided in Table 6-2. Table 6-2. VADJ to VOUT VOUT (V) 2.75 2.70 2.65 2.60 VADJ Value 0x1F 0x00 0x01 0x02 VOUT (V) 2.55 2.50 2.45 2.40 VADJ Value 0x03 0x04 0x05 0x06-0x3F VOUT (V) 2.35 2.30 2.25 Reserved VADJ Value 0x1B 0x1C 0x1D 0x1E 61 Preliminary March 22, 2006 LM3S101 Data Sheet Register 10: Software Reset Control 0 (SRCR0), offset 0x040 Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register (see page 56). Software Reset Control 0 (SRCR0) Offset 0x040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 R/W 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 WDT R/W 0 RO 0 reserved RO 0 RO 0 Bit/Field 31:4 3 2:0 Name reserved WDT reserved Type RO R/W RO Reset 0 0 0 Description Reserved bits return an indeterminate value, and should never be changed. Reset control for the Watchdog unit. Read as 0. March 22, 2006 Preliminary 62 System Control Register 11: Software Reset Control 1 (SRCR1), offset 0x044 Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register (see page 57). Software Reset Control 1 (DC1) Offset 0x044 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 COMP1 COMP0 R/W 0 9 R/W 0 8 RO 0 7 RO 0 6 reserved RO 0 5 RO 0 4 RO 0 3 RO 0 2 GPTM1 GPTM0 R/W 0 1 R/W 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 SSI R/W 0 RO 0 reserved RO 0 RO 0 UART0 R/W 0 Bit/Field 31:26 25 24 23:18 17 16 15:5 4 3:1 0 Name reserved COMP1 COMP0 reserved GPTM1 GPTM0 reserved SSI reserved UART0 Type RO R/W R/W RO R/W R/W RO R/W RO R/W Reset 0 0 0 0 0 0 0 0 0 0 Description Reserved bits return an indeterminate value, and should never be changed. Reset control for analog comparator 1. Reset control for analog comparator 0. Reserved bits return an indeterminate value, and should never be changed. Reset control for General-Purpose Timer module 1. Reset control for General-Purpose Timer module 0. Reserved bits return an indeterminate value, and should never be changed. Reset control for the SSI units. Reserved bits return an indeterminate value, and should never be changed. Reset control for the UART0 module. 63 Preliminary March 22, 2006 LM3S101 Data Sheet Register 12: Software Reset Control 2 (SRCR2), offset 0x048 Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register (see page 59). Software Reset Control (SRCR2) Offset 0x048 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PORTC PORTB PORTA R/W 0 R/W 0 R/W 0 Bit/Field 31:3 2 1 0 Name reserved PORTC PORTB PORTA Type RO R/W R/W R/W Reset 0 0 0 0 Description Reserved bits return an indeterminate value, and should never be changed. Reset control for GPIO Port C. Reset control for GPIO Port B. Reset control for GPIO Port A. March 22, 2006 Preliminary 64 System Control Register 13: Raw Interrupt Status (RIS), offset 0x050 Central location for system control raw interrupts. These are set and cleared by hardware. Raw Interrupt Status (RIS) Offset 0x050 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PLLLRIS CLRIS BOFRIS MOFRIS LDORIS BORRIS PLLFRIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:7 6 Name reserved PLLLRIS Type RO RO Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. PLL Lock Raw Interrupt Status This bit is set when the PLL TREADY Timer asserts. 5 CLRIS RO 0 Current Limit Raw Interrupt Status This bit is set if the LDO's CLE output asserts. 4 BOFRIS RO 0 Boot Oscillator Fault Raw Interrupt Status This bit is set if a boot oscillator fault is detected. 3 MOFRIS RO 0 Main Oscillator Fault Raw Interrupt Status This bit is set if a main oscillator fault is detected. 2 LDORIS RO 0 LDO Power Unregulated Raw Interrupt Status This bit is set if a LDO voltage is unregulated. 1 BORRIS RO 0 Brown-Out Reset Raw Interrupt Status This bit is the raw interrupt status for any brown-out conditions. If set, a brown-out condition was detected. An interrupt is reported if the BORIM bit in the IMC register is set and the BORIOR bit in the PBORCTL register is cleared. 0 PLLFRIS RO 0 PLL Fault Raw Interrupt Status This bit is set if a PLL fault is detected (stops oscillating). 65 Preliminary March 22, 2006 LM3S101 Data Sheet Register 14: Interrupt Mask Control (IMC), offset 0x054 Central location for system control interrupt masks. Interrupt Mask Control (IMC) Offset 0x054 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PLLLIM R/W 0 CLIM R/W 0 BOFIM MOFIM LDOIM BORIM PLLFIM R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:7 6 Name reserved PLLLIM Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. PLL Lock Interrupt Mask This bit specifies whether a current limit detection is promoted to a controller interrupt. If set, an interrupt is generated if PLLLRIS is set; otherwise, an interrupt is not generated. 5 CLIM R/W 0 Current Limit Interrupt Mask This bit specifies whether a current limit detection is promoted to a controller interrupt. If set, an interrupt is generated if CLRIS is set; otherwise, an interrupt is not generated. 4 BOFIM R/W 0 Boot Oscillator Fault Interrupt Mask This bit specifies whether a boot oscillator fault detection is promoted to a controller interrupt. If set, an interrupt is generated if BOFRIS is set; otherwise, an interrupt is not generated. 3 MOFIM R/W 0 Main Oscillator Fault Interrupt Mask This bit specifies whether a main oscillator fault detection is promoted to a controller interrupt. If set, an interrupt is generated if MOFRIS is set; otherwise, an interrupt is not generated. 2 LDOIM R/W 0 LDO Power Unregulated Interrupt Mask This bit specifies whether an LDO unregulated power situation is promoted to a controller interrupt. If set, an interrupt is generated if LDORIS is set; otherwise, an interrupt is not generated. March 22, 2006 Preliminary 66 System Control Bit/Field 1 Name BORIM Type R/W Reset 0 Description Brown-Out Reset Interrupt Mask This bit specifies whether a brown-out condition is promoted to a controller interrupt. If set, an interrupt is generated if BORRIS is set; otherwise, an interrupt is not generated. 0 PLLFIM R/W 0 PLL Fault Interrupt Mask This bit specifies whether a PLL fault detection is promoted to a controller interrupt. If set, an interrupt is generated if PLLFRIS is set; otherwise, an interrupt is not generated. 67 Preliminary March 22, 2006 LM3S101 Data Sheet Register 15: Masked Interrupt Status and Clear (MISC), offset 0x058 Central location for system control result of RIS AND IMC to generate an interrupt to the controller. All of the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS register. Masked Interrupt Status and Clear (MISC) Offset 0x058 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PLLLMIS CLMIS BOFMIS MOFMIS LDOMIS BORMIS PLLFMIS R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 Bit/Field 31:7 6 Name reserved PLLLMIS Type RO R/W1C Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. PLL Lock Masked Interrupt Status This bit is set when the PLL TREADY timer asserts. The interrupt is cleared by writing a 1 to this bit. 5 CLMIS R/W1C 0 Current Limit Masked Interrupt Status This bit is set if the LDO's CLE output asserts. The interrupt is cleared by writing a 1 to this bit. 4 BOFMIS R/W1C 0 Boot Oscillator Fault Masked Interrupt Status This bit is set if a boot oscillator fault is detected. The interrupt is cleared by writing a 1 to this bit. 3 MOFMIS R/W1C 0 Main Oscillator Fault Masked Interrupt Status This bit is set if a main oscillator fault is detected. The interrupt is cleared by writing a 1 to this bit. 2 LDOMIS R/W1C 0 LDO Power Unregulated Masked Interrupt Status This bit is set if LDO power is unregulated. The interrupt is cleared by writing a 1 to this bit. 1 BORMIS R/W1C 0 Brown-Out Reset Masked Interrupt Status This bit is the masked interrupt status for any brown-out conditions. If set, a brown-out condition was detected. An interrupt is reported if the BORIM bit in the IMC register is set and the BORIOR bit in the PBORCTL register is cleared. The interrupt is cleared by writing a 1 to this bit. 0 PLLFMIS R/W1C 0 PLL Fault Masked Interrupt Status This bit is set if a PLL fault is detected (stops oscillating). The interrupt is cleared by writing a 1 to this bit. March 22, 2006 Preliminary 68 System Control Register 16: Reset Cause (RESC), offset 0x05C This field specifies the cause of the reset event to software. The reset value is determined by the cause of the reset. When an external reset is the cause (EXT is set), all other reset bits are cleared. However, if the reset is due to any other cause, the remaining bits are sticky, allowing software to see all causes. Reset Cause (RESC) Offset 0x05C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 LDO R/W - SW R/W - WDT R/W - BOR R/W - POR R/W - EXT R/W - Bit/Field 31:6 5 4 3 2 1 0 Name reserved LDO SW WDT BOR POR EXT Type RO R/W R/W R/W R/W R/W R/W Reset 0 - Description Reserved bits return an indeterminate value, and should never be changed. When set to 1, LDO power OK lost is the cause of the reset event. When set to 1, a software reset is the cause of the reset event. When set to 1, a watchdog reset is the cause of the reset event. When set to 1, a brown-out reset is the cause of the reset event. When set to 1, a power-on reset is the cause of the reset event. When set to 1, an external reset (RST assertion) is the cause of the reset event. 69 Preliminary March 22, 2006 LM3S101 Data Sheet Register 17: Run-Mode Clock Configuration (RCC), offset 0x060 This register is defined to provide source control and frequency speed. Run-Mode Clock Configuration (RCC) Offset 0x060 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 ACG R/W 0 11 R/W 1 10 R/W 1 9 SYSDIV R/W 1 8 R/W 1 7 USESYS R/W 0 6 RO 0 5 RO 0 4 reserved RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 PWRDN R/W 1 OEN R/W 1 BYPASS R/W 1 PLLVER R/W 0 R/W 1 R/W 0 XTAL R/W 1 R/W 1 R/W 0 OSCSRC R/W 0 BOSCVERMOSCVER R/W 0 R/W 0 RO 0 reserved RO 0 Bit/Field 31:28 27 Name Reserved ACG Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. Auto Clock Gating This bit specifies whether the system uses the Sleep-Mode Clock Gating Control (SCGCn) registers (see page 75) and Deep-Sleep-Mode Clock Gating Control (DCGCn) registers (see page 75) if the controller enters a Sleep or Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers are used to control the clocks distributed to the peripherals when the controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating Control (RCGCn) registers (see page 75) are used when the controller enters a sleep mode. The RCGCn registers are always used to control the clocks in Run mode. This allows peripherals to consume less power when the controller is in a sleep mode and the peripheral is unused. March 22, 2006 Preliminary 70 System Control Bit/Field 26:23 Name SYSDIV Type R/W Reset 0xF Description System Clock Divisor Specifies which divisor is used to generate the system clock from the PLL output (200 MHz). Binary Value 00001000 1001 1010 1011 1100 1101 1110 1111 Divisor (BYPASS=1) reserved /10 /11 /12 /13 /14 /15 /16 Frequency (BYPASS=0) reserved 20 MHz 18.18 MHz 16.67 MHz 15.38 MHz 14.29 MHz 13.33 MHz 12.5 MHz (default) When reading the Run-Mode Clock Configuration (RCC) register (see page 70), the SYSDIV value will be MINSYSDIV if a lower divider was requested and the PLL is being used. This lower value will be allowed to divide a nonPLL source. 22 USESYS R/W 0 Use the system clock divider as the source for the system clock. The system clock divider is forced to be used when the PLL is selected as the source. Read as 1. PLL Power Down This bit connects to the PLL PWRDN input. The reset value of 1 powers down the PLL. See Table 6-4 on page 73 for PLL mode control. 12 OEN R/W 1 PLL Output Enable This bit specifies whether the PLL output driver is enabled. If cleared, the driver transmits the PLL clock to the output. Otherwise, the PLL clock does not oscillate outside the PLL module. Note: 11 BYPASS R/W 1 Both PWRDN and OEN must be cleared to run the PLL. 21:14 13 reserved PWRDN RO R/W 1 1 PLL Bypass Chooses whether the system clock is derived from the PLL output or the OSC source. If set, the clock that drives the system is the OSC source. Otherwise, the clock that drives the system is the PLL output clock divided by the system divider. 71 Preliminary March 22, 2006 LM3S101 Data Sheet Bit/Field 10 Name PLLVER Type R/W Reset 0x0 Description PLL Verification This bit controls the PLL verification timer function. If set, the verification timer is enabled and an interrupt is generated if the PLL becomes inoperative. Otherwise, the verification timer is not enabled. 9:6 XTAL R/W 0xB This field specifies the crystal value attached to the main oscillator. The encoding for this field is provided in Table 6-3 on page 72. Oscillator-Related Bits 5:4 OSCSRC R/W 0x0 Picks among the four input sources for the OSC leg. The values are: Value 00 01 10 11 3 BOSCVER R/W 0x0 Input Source Main oscillator Boot oscillator Boot oscillator / 4 (this is necessary if used as input to PLL) reserved This bit controls the boot oscillator verification timer function. If set, the verification timer is enabled and an interrupt is generated if the timer becomes inoperative. Otherwise, the verification timer is not enabled. This bit controls the main oscillator verification timer function. If set, the verification timer is enabled and an interrupt is generated if the timer becomes inoperative. Otherwise, the verification timer is not enabled. Reserved bits return an indeterminate value, and should never be changed. 2 MOSCVER R/W 0x0 1:0 reserved RO 0x0 Table 6-3. Default Crystal Field Values and PLL Programming Crystal Frequency (MHz) reserved 3.579545 MHz 3.6864 MHz 4 MHz 4.096 MHz 4.9152 MHz 5 MHz Crystal Number (XTAL Binary Value) 0000-0011 0100 0101 0110 0111 1000 1001 March 22, 2006 Preliminary 72 System Control Table 6-3. Default Crystal Field Values and PLL Programming Crystal Frequency (MHz) 5.12 MHz 6 MHz (reset value) 6.144 MHz 7.3728 MHz 8 MHz 8.192 MHz Crystal Number (XTAL Binary Value) 1010 1011 1100 1101 1110 1111 Table 6-4. PWRDN 1 0 PLL Mode Control OEN X 0 Mode Power down Normal 73 Preliminary March 22, 2006 LM3S101 Data Sheet Register 18: XTAL to PLL Translation (PLLCFG), offset 0x064 This register provides a means of translating external crystal frequencies into the appropriate PLL settings. This register is initialized during the reset sequence and updated anytime that the XTAL field changes in the Run-Mode Clock Configuration (RCC) register (see page 70). XTAL to PLL Translation (PLLCFG) Offset 0x064 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 OD Type Reset RO RO RO RO RO RO - F RO RO RO RO RO RO RO - R RO RO RO - Bit/Field 31:16 15:14 13:5 4:0 Name reserved OD F R Type RO RO RO RO Reset 0 - Description Reserved bits return an indeterminate value, and should never be changed. This field specifies the value supplied to the PLL's OD input. This field specifies the value supplied to the PLL's F input. This field specifies the value supplied to the PLL's R input. March 22, 2006 Preliminary 74 System Control Register 19: Run-Mode Clock Gating Control 0 (RCGC0), offset 0x100 Register 20: Sleep-Mode Clock Gating Control 0 (SCGC0), offset 0x110 Register 21: Deep-Sleep-Mode Clock Gating Control 0 (DCGC0), offset 0x120 These registers control the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register (see page 70) specifies that the system uses sleep modes. The bit diagram for these three registers is shown below. Bits have the same definitions as DC1 (see page 56) and use DC1 as the mask. Run-Mode, Sleep-Mode and Deep-Sleep-Mode Clock Gating Control 0 (RCGC0, SCG0, and DCGC0) Offset 0x100, 0x110, 0x120 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 WDT R/W 0 SWO R/W 0 SWD R/W 0 JTAG R/W 1 75 Preliminary March 22, 2006 LM3S101 Data Sheet Register 22: Run-Mode Clock Gating Control 1 (RCGC1), offset 0x104 Register 23: Sleep-Mode Clock Gating Control 1 (SCGC1), offset 0x114 Register 24: Deep-Sleep-Mode Clock Gating Control 1 (DCGC1), offset 0x124 These registers control the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register (see page 70) specifies that the system uses sleep modes. The bit diagram for these three registers is shown below. Bits have the same definitions as DC2 (see page 57) and use DC2 as the mask. Run-Mode, Sleep-Mode, and Deep-Sleep-Mode Clock Gating Control 1 (RCGC1, SCGC1, and DCGC1) Offset 0x104, 0x114, and 0x124 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 COMP1 COMP0 R/W 0 9 R/W 0 8 RO 0 7 RO 0 6 reserved RO 0 5 RO 0 4 RO 0 3 RO 0 2 GPTM1 GPTM0 R/W 0 1 R/W 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 SSI R/W 0 RO 0 reserved RO 0 RO 0 UART0 R/W 0 March 22, 2006 Preliminary 76 System Control Register 25: Run-Mode Clock Gating Control 2 (RCGC2), offset 0x108 Register 26: Sleep-Mode Clock Gating Control 2 (SCGC2), offset 0x118 Register 27: Deep-Sleep-Mode Clock Gating Control 2 (DCGC2), offset 0x128 These registers control the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register (see page 70) specifies that the system uses sleep modes. The bit diagram for these three registers is shown below. Bits have the same definitions as DC4 (see page 59) and use DC4 as the mask. Run-Mode, Sleep-Mode, and Deep-Sleep-Mode Clock Gating Control 2 (RCGC2, SCGC2, and DCGC2) Offset 0x108, 0x118, and 0x128 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PORTC PORTB PORTA R/W 0 R/W 0 R/W 0 77 Preliminary March 22, 2006 LM3S101 Data Sheet Register 28: Clock Verification Clear (CLKVCLR), offset 0x150 This register is provided as a means of clearing the clock verification circuits by software. Since the clock verification circuits force a known good clock to control the process, the controller is allowed the opportunity to solve the problem and clear the verification fault. This register clears all clock verification faults. To clear a clock verification fault, the VERCLR bit must be set and then cleared by software. This bit is not self-clearing. Clock Verification Clear (CLKVCLR) Offset 0x150 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 VERCLR R/W 0 Bit/Field 31:1 0 Name Reserved VERCLR Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. Clear clock verification faults. March 22, 2006 Preliminary 78 System Control Register 29: Allow Unregulated LDO to Reset the Part (LDOARST), offset 0x160 This register is provided as a means of allowing the LDO to reset the part if the voltage goes unregulated. Use this register to choose whether to automatically reset the part if the LDO goes unregulated, based on the design tolerance for LDO fluctuation. Allow Unregulated LDO to Reset the Part (LDOARST) Offset 0x160 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 LDOARST R/W 0 Bit/Field 31:1 0 Name Reserved LDOARST Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. Set to 1 to allow unregulated LDO output to reset the part. 79 Preliminary March 22, 2006 LM3S101 Data Sheet 7 Internal Memory The LM3S101 comes with 2 KB of bit-banded SRAM and 8 KB of flash memory. The flash controller provides a user-friendly interface, making flash programming a simple task. Flash protection can be applied to the flash memory on a 2-KB block basis. 7.1 Block Diagram Figure 7-1. Flash Block Diagram Flash Timing USECRL ICode Cortex-M3 DCode Flash Control FMA FMD FMC Flash Array System Bus FCRIS FCIM FCMISC APB Bridge Flash Protection FMPRE SRAM Array FMPPE 7.2 7.2.1 Functional Description This section describes the functionality of both memories. SRAM Memory The internal SRAM of the Stellaris devices is located at address 0x20000000 of the device memory map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has introduced bit-banding technology in the new Cortex-M3 processor. With a bit-bandenabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. The bit-band alias is calculated by using the formula: bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4) March 22, 2006 Preliminary 80 Internal Memory For example, if bit 3 at address 0x20001000 is to be modified, the bit-band alias is calculated as: 0x22000000 + (0x1000 * 32) + (3 * 4) = 0x2202000C With the alias address calculated, an instruction performing a read/write to address 0x2202000C allows direct access to only bit 3 of the byte at address 0x20001000. For details about bit-banding, please refer to Chapter 4, "Memory Map" in the ARM(R) CortexTM-M3 Technical Reference Manual. 7.2.2 Flash Memory The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of 2KB blocks that can be individually protected. The blocks can be marked as read-only or executeonly, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. 7.2.2.1 Flash Memory Timing The timing for the flash is automatically handled by the flash controller. However, in order to do so, it must know the clock rate of the system in order to time its internal signals properly. The number of clock cycles per microsecond must be provided to the flash controller for it to accomplish this timing. It is software's responsibility to keep the flash controller updated with this information via the U Second Reload (USECRL) register (see page 85). On reset, USECRL is loaded with a value that will configure the flash timing so that it works with the selected crystal value. If software changes the system operating frequency, the new operating frequency must be loaded into USECRL before any flash modifications are attempted. For example, if the device is operating at a speed of 20 MHz, a value of 0x13 must be written to the USECRL register. 7.2.2.2 Flash Memory Protection The user is provided two forms of flash protection per 2-KB flash blocks in two 32-bit wide registers. The protection policy for each form is controlled by individual bits (per policy per block) in the FMPPE and FMPRE registers (see page 84). Flash Memory Protection Program Enable (FMPPE): If set, the block may be programmed (written) or erased. If cleared, the block may not be changed. Flash Memory Protection Read Enable (FMPRE): If set, the block may be executed or read by software or debuggers. If cleared, the block may only be executed. The contents of the memory block are prohibited from being accessed as data and traversing the data bus. The policies may be combined as shown in Table 7-1. Table 7-1. FMPPE 0 1 Flash Protection Policy Combinations FMPRE 0 0 Protection Execute-only protection. The block may only be executed and may not be written or erased. This mode is used to protect code. The block may be written, erased or executed, but not read. This combination is unlikely to be used. 81 Preliminary March 22, 2006 LM3S101 Data Sheet Table 7-1. FMPPE 0 Flash Protection Policy Combinations FMPRE 1 Protection Read-only protection. The block may be read or executed but may not be written or erased. This mode is used to lock the block from further modification while allowing any read or execute access. No protection. The block may be written, erased, executed or read. 1 1 An access that attempts to program or erase a PE-protected block is prohibited. A controller interrupt may be optionally generated (by setting the AMASK bit in the FIM register) to alert software developers of poorly behaving software during the development and debug phases. An access that attempts to read an RE-protected block is prohibited. Such accesses return data filled with all 0s. A controller interrupt may be optionally generated to alert software developers of poorly behaving software during the development and debug phases. The factory settings for the FMPRE and FMPPE registers are a value of 1 for all implemented banks. This implements a policy of open access and programmability. The register bits may be changed by writing the specific register bit. The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. 7.2.2.3 Flash Memory Programming Writing the flash memory requires that the code be executed out of SRAM to avoid corrupting or interrupting the bus timing. Flash pages can be erased on a page basis (1 KB in size), or by performing a mass erase of the entire flash. All erase and program operations are performed using the Flash Memory Address (FMA), Flash Memory Data (FMD) and Flash Memory Control (FMC) registers. See section 7.3 for examples. 7.3 Initialization and Configuration This section shows examples for using the flash controller to perform various operations on the contents of the flash memory. 7.3.1 Changing Flash Protection Bits As discussed in Section 7.2.2.2, changes to the protection bits must be committed before they take effect. The sequence to change and commit a bit in software is as follows: 1. The Flash Memory Protection Read Enable (FMPRE) and Flash Memory Protection Program Enable (FMPPE) registers are written, changing the intended bit(s). The action of these changes can be tested by software while in this state. 2. The Flash Memory Address (FMA) register (see page 86) bit 0 is set to 1 if the FMPPE register is to be committed; otherwise, a 0 commits the FMPRE register. 3. The Flash Memory Control (FMC) register (see page 88) is written with the COMT bit set. This initiates a write sequence and commits the changes. 7.3.2 Flash Programming The Stellaris devices provide a user-friendly interface for flash programming. All erase/program operations are handled via three registers: FMA, FMD and FMC. March 22, 2006 Preliminary 82 Internal Memory The flash is programmed using the following sequence: 1. Write source data to the FMD register. 2. Write the target address to the FMA register. 3. Write the flash write key and the WRITE bit (a value of 0xA4420001) to the FMC register. 4. Poll the FMC register until the WRITE bit is cleared. To perform an erase of a 1-KB page: 1. Write the page address to the FMA register. 2. Write the flash write key and the ERASE bit (a value of 0xA4420002) to the FMC register. 3. Poll the FMC register until the ERASE bit is cleared. To perform a mass erase of the flash: 1. Write the flash write key and the MERASE bit (a value of 0xA4420004) to the FMC register. 2. Poll the FMC register until the MERASE bit is cleared. 7.4 Register Map Table 7-2 lists the Flash memory and control registers. All addresses given are relative to the Flash control base address of 0x400FD000, except for FMPRE and FMPPE, which are relative to the System Control base address of 0x400FE000. Table 7-2. Offset 0x130a 0x134a 0X140a 0x000 0x004 0x008 0x00C 0x010 0x014 Flash Register Map Name FMPRE FMPPE USECRL FMA FMD FMC FCRIS FCIM FCMISC Reset 0x0F 0x0F 0x13 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Type R/W0 R/W0 R/W R/W R/W R/W RO R/W R/W1C Description Flash memory read protect Flash memory program protect U second reload Flash memory address Flash memory data Flash memory control Flash controller raw interrupt status Flash controller interrupt mask Flash controller masked interrupt status and clear See page 84 84 85 86 87 88 90 91 92 a. Relative to System Control base address of 0x400FE000. 7.5 Register Descriptions The remainder of this section lists and describes the Flash Memory registers, in numerical order by address offset. 83 Preliminary March 22, 2006 LM3S101 Data Sheet Register 1: Flash Memory Protection Read Enable (FMPRE), offset 0x130 Register 2: Flash Memory Protection Program Enable (FMPPE), offset 0x134 Note: Offset is relative to System Control base address of 0x400FE000 These registers store the read-only (FMPRE) and execute-only (FMPPE) protection bits for each 2 KB flash block. This register is loaded during the power-on reset sequence. The factory settings for the FMPRE and FMPPE registers are a value of 1 for all implemented banks. This implements a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see "Flash Memory Protection" on page 81. Flash Memory Protection Read Enable and Program Enable (FMPRE and FMPPE) Offset 0x130 and 0x134 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Block3 R/W0 1 Block2 R/W0 1 Block1 R/W0 1 Block0 R/W0 1 Bit/Field 31:4 3:0 Name reserved Block3Block0 Type RO R/W0 Reset 0 0x0F Description Reserved bits return an indeterminate value, and should never be changed. Enable 2-KB flash blocks to be written or erased (FMPPE register), or executed or read (FMPRE register). The policies may be combined as shown in Table 7-1 on page 81. March 22, 2006 Preliminary 84 Internal Memory Register 3: U Second Reload (USECRL), offset 0x140 Note: Offset is relative to System Control base address of 0x400FE000 This register is provided as a means of creating a 1 usec tick divider reload value for the flash controller. The internal flash has specific minimum and maximum requirement on the length of time the high voltage write pulse can be applied. It is required that this register contain the operating frequency (in MHz -1) whenever the flash is being erased or programmed. The user is required to change this value if the clocking conditions are changed for a flash erase/program operation. Usec Reload (USECRL) Offset 0x140 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 USEC R/W 1 R/W 0 R/W 0 R/W 1 R/W 1 Bit/Field 31:8 7:0 Name reserved USEC Type RO R/W Reset 0 0x13 Description Reserved bits return an indeterminate value, and should never be changed. MHz -1 of the controller clock when the flash is being erased or programmed. USEC should be set to 0x13 (19 MHz) whenever the flash is being erased or programmed. 85 Preliminary March 22, 2006 LM3S101 Data Sheet Register 4: Flash Memory Address (FMA), offset 0x000 During a write operation, this register contains a 4-byte-aligned address and specifies where the data is written. During erase operations, this register contains a 1 KB-aligned address and specifies which page is erased. Note that the alignment requirements must be met by software or the results of the operation are unpredictable. Flash Memory Address (FMA) Offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 OFFSET R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:12 11:0 Name reserved OFFSET Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. Address offset in flash where operation is performed. March 22, 2006 Preliminary 86 Internal Memory Register 5: Flash Memory Data (FMD), offset 0x004 This register contains the data to be written during the programming cycle or read during the read cycle. Note that the contents of this register are undefined for a read access of an execute-only block. This register is not used during the erase cycles. Flash Memory Data (FMD) Offset 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DATA Type Reset R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 R/W 0 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 DATA Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:0 Name DATA Type R/W Reset 0 Description Data value for write operation. 87 Preliminary March 22, 2006 LM3S101 Data Sheet Register 6: Flash Memory Control (FMC), offset 0x008 When this register is written, the flash controller initiates the appropriate access cycle for the location specified by the Flash Memory Address (FMA) register (see page 86). If the access is a write access, the data contained in the Flash Memory Data (FMD) register (see page 87) is written. This is the final register written and initiates the memory operation. There are four control bits in the lower byte of this register that, when set, initiate the memory operation. The most used of these register bits are the ERASE and WRITE bits. It is a programming error to write multiple control bits and the results of such an operation are unpredictable. Flash Memory Control (FMC) Offset 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WRKEY Type Reset WO 0 15 WO 0 14 WO 0 13 WO 0 12 WO 0 11 WO 0 10 WO 0 9 WO 0 8 WO 0 7 WO 0 6 WO 0 5 WO 0 4 WO 0 3 WO 0 2 WO 0 1 WO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 COMT MERASE ERASE WRITE R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:16 Name WRKEY Type WO Reset 0 Description This field contains a write key, which is used to minimize the incidence of accidental flash writes. The value 0xA442 must be written into this field for a write to occur. Writes to the FMC register without this WRKEY value are ignored. A read of this field returns the value 0. Reserved bits return an indeterminate value, and should never be changed. Commit (write) of register value to non-volatile storage. A write of 0 has no effect on the state of this bit. If read, the state of the previous commit access is provided. If the previous commit access is complete, a 0 is returned; otherwise, if the commit access is not complete, a 1 is returned. This can take up to 50 s. 15:4 3 reserved COMT RO R/W 0 0 2 MERASE R/W 0 Mass erase flash memory If this bit is set, the flash main memory of the device is all erased. A write of 0 has no effect on the state of this bit. If read, the state of the previous mass erase access is provided. If the previous mass erase access is complete, a 0 is returned; otherwise, if the previous mass erase access is not complete, a 1 is returned. This can take up to 250 ms. March 22, 2006 Preliminary 88 Internal Memory Bit/Field 1 Name ERASE Type R/W Reset 0 Description Erase a page of flash memory If this bit is set, the page of flash main memory as specified by the contents of FMA is erased. A write of 0 has no effect on the state of this bit. If read, the state of the previous erase access is provided. If the previous erase access is complete, a 0 is returned; otherwise, if the previous erase access is not complete, a 1 is returned. This can take up to 25 ms. 0 WRITE R/W 0 Write a word into flash memory If this bit is set, the data stored in FMD is written into the location as specified by the contents of FMA. A write of 0 has no effect on the state of this bit. If read, the state of the previous write update is provided. If the previous write access is complete, a 0 is returned; otherwise, if the write access is not complete, a 1 is returned. This can take up to 50 s. 89 Preliminary March 22, 2006 LM3S101 Data Sheet Register 7: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C This register indicates that the flash controller has an interrupt condition. An interrupt is only signaled if the corresponding FCIM register bit is set. Flash Controller Raw Interrupt Status (FCRIS) Offset 0x00C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PRIS RO 0 ARIS RO 0 Bit/Field 31:2 1 Name reserved PRIS Type RO RO Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. Programming Raw Interrupt Status This bit indicates the current state of the programming cycle. If set, the programming cycle completed; if cleared, the programming cycle has not completed. Programming cycles are either write or erase actions generated through the Flash Memory Control (FMC) register bits (see page 88). 0 ARIS RO 0 Access Raw Interrupt Status This bit indicates if the flash was improperly accessed. If set, the program tried to access the flash counter to the policy as set in the Flash Memory Protection Read Enable (FMPRE) and Flash Memory Protection Program Enable (FMPPE) register (see page 84). Otherwise, no access has tried to improperly access the flash. March 22, 2006 Preliminary 90 Internal Memory Register 8: Flash Controller Interrupt Mask (FCIM), offset 0x010 This register controls whether the flash controller generates interrupts to the controller. Flash Controller Interrupt Mask (FCIM) Offset 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PMASK AMASK R/W 0 R/W 0 Bit/Field 31:2 1 Name reserved PMASK Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. Programming Interrupt Mask This bit controls the reporting of the programming raw interrupt status to the controller. If set, a programminggenerated interrupt is promoted to the controller. Otherwise, interrupts are recorded but suppressed from the controller. 0 AMASK R/W 0 Access Interrupt Mask This bit controls the reporting of the access raw interrupt status to the controller. If set, an access-generated interrupt is promoted to the controller. Otherwise, interrupts are recorded but suppressed from the controller. 91 Preliminary March 22, 2006 LM3S101 Data Sheet Register 9: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 This register provides two functions. First, it reports the cause of an interrupt by indicating which interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the interrupt reporting. Flash Controller Masked Interrupt Status and Clear (FCMISC) Offset 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PMISC R/W1C 0 AMISC R/W1C 0 Bit/Field 31:2 1 Name reserved PMISC Type RO R/W1C Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. Programming Masked Interrupt Status and Clear This bit indicates whether an interrupt was signaled because a programming cycle completed and was not masked. This bit is cleared by writing a 1. The PRIS bit in the FCRIS register (see page 90) is also cleared when the PMISC bit is cleared. 0 AMISC R/W1C 0 Access Masked Interrupt Status and Clear This bit indicates whether an interrupt was signaled because an improper access was attempted and was not masked. This bit is cleared by writing a 1. The ARIS bit in the FCRIS register is also cleared when the AMISC bit is cleared. March 22, 2006 Preliminary 92 General-Purpose Input/Outputs (GPIOs) 8 General-Purpose Input/Outputs (GPIOs) The GPIO module is composed of three physical GPIO blocks, each corresponding to an individual GPIO port (Port A, Port B, and Port C). The GPIO module is FiRM-compliant and supports 2 to 18 programmable input/output pins, depending on the peripherals being used. The GPIO module has the following features: Programmable control for GPIO interrupts: - Interrupt generation masking - Edge-triggered on rising, falling, or both - Level-sensitive on High or Low values Bit masking in both read and write operations through address lines Programmable control for GPIO pad configuration: - Weak pull-up or pull-down resistors - 2-mA, 4-mA, and 8-mA pad drive - Slew rate control for the 8-mA drive - Open drain enables - Digital input enables 93 Preliminary March 22, 2006 LM3S101 Data Sheet 8.1 Block Diagram Figure 8-1. GPIO Module Block Diagram PA0 GPIO Port A PA1 PA2 PA3 PA4 PA5 U0Rx U0Tx SSIClk SSIFss SSIRx SSITx SSI UART0 PB0 PB1 GPIO Port B PB2 PB3 PB4 PB5 PB6 PB7 CCP0 32KHz Timer 0 Timer 1 C0C0o/C1C0+ Analog Comparators PC1 PC2 PC3 GPIO Port C PC0 TCK/SWCLK TMS/SWDIO TDI TDO/SWO TRST JTAG 8.2 Functional Description Important: All GPIO pins are inputs by default (GPIODIR=0 and GPIOAFSEL=0), with the exception of the five JTAG pins (PB7 and PC[3:0]. The JTAG pins default to their JTAG functionality (GPIOAFSEL=1). Asserting a Power-On-Reset (POR) or an external reset (RST) puts both groups of pins back to their default state. Each GPIO port is a separate hardware instantiation of the same physical block (see Figure 8-2). The LM3S101 microcontroller contains three of these physical GPIO blocks. March 22, 2006 Preliminary 94 General-Purpose Input/Outputs (GPIOs) Figure 8-2. GPIO Port Block Diagram Function Selection GPIOAFSEL Alternate Input Alternate Output Alternate Output Enable GPIO Input GPIO Output GPIO Output Enable D E M U X M U X Pad Input Pad Output I/O Data GPIODATA GPIODIR I/O Pad Package I/O Pin M U X Pad Output Enable Interrupt Control GPIOIS GPIOIBE GPIOIEV GPIOIM GPIORIS GPIOMIS GPIOICR I/O Pad Control GPIODR2R GPIODR4R GPIODR8R GPIOSLR GPIOPUR GPIOPDR GPIOODR GPIODEN Interrupt Identification Registers GPIOPeriphID0 GPIOPeriphID1 GPIOPeriphID2 GPIOPeriphID3 GPIOPeriphID4 GPIOPeriphID5 GPIOPeriphID6 GPIOPeriphID7 GPIOPCellID0 GPIOPCellID1 GPIOPCellID2 GPIOPCellID3 8.2.1 Data Register Operation To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the GPIO Data (GPIODATA) register (see page 100) by using bits [9:2] of the address bus as a mask. This allows software drivers to modify individual GPIO pins in a single instruction, without affecting the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA register covers 256 locations in the memory map. During a write, if the address bit associated with that data bit is set to 1, the value of the GPIODATA register is altered. If it is cleared to 0, it is left unchanged. For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in Figure 8-3, where u is data unchanged by write. Figure 8-3. GPIODATA Write Example ADDR[9:2] 0x098 0xEB GPIODATA 9 0 1 u 7 8 0 1 u 6 7 1 1 1 5 6 0 0 u 4 5 0 1 u 3 4 1 0 0 2 3 1 1 1 1 2 0 1 u 0 1 0 0 0 95 Preliminary March 22, 2006 LM3S101 Data Sheet During a read, if the address bit associated with the data bit is set to 1, the value is read. If the address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value. For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 8-4. Figure 8-4. GPIODATA Read Example ADDR[9:2] 0x0C4 GPIODATA Returned Value 9 0 1 0 7 8 0 0 0 6 7 1 1 1 5 6 1 1 1 4 5 0 1 0 3 4 0 1 0 2 3 0 1 0 1 2 1 0 0 0 1 0 0 0 8.2.2 Data Direction The GPIO Direction (GPIODIR) register (see page 101) is used to configure each individual pin as an input or output. 8.2.3 Interrupt Operation The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these registers, it is possible to select the source of the interrupt, its polarity, and the edge properties. When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external source holds the level constant for the interrupt to be recognized by the controller. Three registers are required to define the edge or sense that causes interrupts: GPIO Interrupt Sense (GPIOIS) register (see page 102) GPIO Interrupt Both Edges (GPIOIBE) register (see page 103) GPIO Interrupt Event (GPIOIEV) register (see page 104) Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 105). When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations: the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers (see pages 106 and 107). As the name implies, the GPIOMIS register only shows interrupt conditions that are allowed to be passed to the controller. The GPIORIS register indicates that a GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the controller. Interrupts are cleared by writing a 1 to the GPIO Interrupt Clear (GPIOICR) register (see page 108). When programming interrupts, the interrupts should be masked (GPIOIM set to 0). Writing any value to an interrupt control register (GPIOIS, GPIOIBE, or GPIOIEV) can generate a spurious interrupt if the corresponding bits are enabled. 8.2.4 Mode Control The GPIO pins can be controlled by either hardware or software. When hardware control is enabled via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 109), the pin state is controlled by its alternate function (that is, the peripheral). Software control corresponds to GPIO mode, where the GPIODATA register is used to read/write the corresponding pins. March 22, 2006 Preliminary 96 General-Purpose Input/Outputs (GPIOs) 8.2.5 Pad Configuration The pad configuration registers allow for GPIO pad configuration by software based on the application requirements. The pad configuration registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR, GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. 8.2.6 Identification The identification registers configured at reset allow software to detect and identify the module as a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as well as the GPIOPCellID0-GPIOPCellID3 registers. 8.3 Initialization and Configuration On reset, all GPIO pins (except for the five JTAG pins) default to general-purpose input mode (GPIODIR and GPIOAFSEL both set to 0). Table 8-1 shows all possible configurations of the GPIO pads and the control register settings required to achieve them. Table 8-2 shows how a rising edge interrupt would be configured for pin 2 of a GPIO port. Table 8-1. Pad Configuration Examples Register Bit Valuea GPIOAFSEL GPIODR2R GPIODR4R GPIODR8R X ? X ? X ? ? ? ? X GPIOODR GPIODEN GPIOPUR GPIOPDR Configuration GPIOSLR X ? X ? X ? ? ? ? X GPIODIR 0 1 0 1 0 X X X X X Digital Input (GPIO) Digital Output (GPIO) Open Drain Input (GPIO) Open Drain Output (GPIO) Analog Input (Comparator) Digital Output (Comparator) Digital Input/Output (UART) Digital Input/Output (SSI) Digital Output (Timer PWM) Digital Input (Timer CCP) 0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 1 ? ? X X 0 ? ? ? ? ? ? ? X X 0 ? ? ? ? ? X ? X ? X ? ? ? ? X X ? X ? X ? ? ? ? X a. X=Ignored (don't care bit) ?=Can be either 0 or 1, depending on the configuration 97 Preliminary March 22, 2006 LM3S101 Data Sheet Table 8-2. Register GPIOIS GPIOIBE GPIOIEV Interrupt Configuration Example Desired Interrupt Event Trigger 0=edge 1=level 0=single edge 1=both edges 0=Low level, or negative edge 1=High level, or positive edge 0=masked 1=not masked Pin 2 Bit Valuea 7 X X 6 X X 5 X X 4 X X 3 X X 2 0 0 1 X X 0 X X X X X X X 1 X X GPIOIM 0 0 0 0 0 1 0 0 a. X=Ignored (don't care bit) 8.4 Register Map Table 8-2 lists the GPIO registers. All addresses given are relative to that GPIO port's base address: GPIO Port A: 0x40004000 GPIO Port B: 0x40005000 GPIO Port C: 0x40006000 The GPIO registers in this chapter are duplicated in each GPIO block, however depending on the block, all eight bits may not be connected to a GPIO pad (see Figure 8-1 on page 94). In those cases, writing to those unconnected bits has no effect and reading those unconnected bits returns no meaningful data. Table 8-3. Offset 0x000 0x400 0x404 0x408 0x40C 0x410 0x414 0x418 0x41C 0x420 GPIO Register Map Name GPIODATA GPIODIR GPIOIS GPIOIBE GPIOIEV GPIOIM GPIORIS GPIOMIS GPIOICR GPIOAFSEL Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 see notea Type R/W R/W R/W R/W R/W R/W RO RO W1C R/W Description Data Data direction Interrupt sense Interrupt both edges Interrupt event Interrupt mask enable Raw interrupt status Masked interrupt status Interrupt clear Alternate function select See page 100 101 102 103 104 105 106 107 108 109 March 22, 2006 Preliminary 98 General-Purpose Input/Outputs (GPIOs) Table 8-3. Offset 0x500 0x504 0x508 0x50C 0x510 0x514 0x518 0x51C 0xFD0 0xFD4 0xFD8 0xFDC 0xFE0 0xFE4 0xFE8 0xFEC 0xFF0 0xFF4 0xFF8 0xFFC GPIO Register Map Name GPIODR2R GPIODR4R GPIODR8R GPIOODR GPIOPUR GPIOPDR GPIOSLR GPIODEN GPIOPeriphID4 GPIOPeriphID5 GPIOPeriphID6 GPIOPeriphID7 GPIOPeriphID0 GPIOPeriphID1 GPIOPeriphID2 GPIOPeriphID3 GPIOPCellID0 GPIOPCellID1 GPIOPCellID2 GPIOPCellID3 Reset 0x000000FF 0x00000000 0x00000000 0x00000000 0x000000FF 0x00000000 0x00000000 0x000000FF 0x00000000 0x00000000 0x00000000 0x00000000 0x00000061 0x00000000 0x00000018 0x00000001 0x0000000D 0x000000F0 0x00000005 0x000000B1 Type R/W R/W R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO RO RO RO RO RO Description 2-mA drive select 4-mA drive select 8-mA drive select Open drain select Pull-up select Pull-down select Slew rate control select Digital input enable Peripheral identification 4 Peripheral identification 5 Peripheral identification 6 Peripheral identification 7 Peripheral identification 0 Peripheral identification 1 Peripheral identification 2 Peripheral identification 3 GPIO PrimeCell identification 0 GPIO PrimeCell identification 1 GPIO PrimeCell identification 2 GPIO PrimeCell identification 3 See page 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 a. The default reset value for the GPIOAFSEL register is 0x00000000 for all GPIO pins, with the exception of the five JTAG pins (PB7 and PC[3:0]. These five pins default to JTAG functionality. Because of this, the default reset value of GPIOAFSEL for GPIO Port B is 0x00000080 while the default reset value of GPIOAFSEL for Port C is 0x0000000F. 8.5 Register Descriptions The remainder of this section lists and describes the GPIO registers, in numerical order by address offset. 99 Preliminary March 22, 2006 LM3S101 Data Sheet Register 1: GPIO Data (GPIODATA), offset 0x000 The GPIODATA register is the data register. In software control mode, values written in the GPIODATA register are transferred onto the GPIO port pins if the respective pins have been configured as outputs through the GPIO Direction (GPIODIR) register (see page 101). In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus bits [9:2], must be High. Otherwise, the bit values remain unchanged by the write. Similarly, the values read from this register are determined for each bit by the mask bit derived from the address used to access the data register, bits [9:2]. Bits that are 1 in the address mask cause the corresponding bits in GPIODATA to be read, and bits that are 0 in the address mask cause the corresponding bits in GPIODATA to be read as 0, regardless of their value. A read from GPIODATA returns the last bit value written if the respective pins are configured as output, or it returns the value on the corresponding input pin when these are configured as inputs. All bits are cleared by a reset. GPIO Data (GPIODATA) Offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 DATA R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit 31:8 7:0 Name reserved DATA Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. GPIO Data This register is virtually mapped to 256 locations in the address space. To facilitate the reading and writing of data to these registers by independent drivers, the data read from and the data written to the registers are masked by the eight address lines ipaddr[9:2]. Reads from this register return its current state. Writes to this register only affect bits that are not masked by ipaddr[9:2] and are configured as outputs. See "Data Register Operation" on page 95 for examples of reads and writes. March 22, 2006 Preliminary 100 General-Purpose Input/Outputs (GPIOs) Register 2: GPIO Direction (GPIODIR), offset 0x400 The GPIODIR register is the data direction register. Bits set to 1 in the GPIODIR register configure the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. All bits are cleared by a reset, meaning all GPIO pins are inputs by default. GPIO Direction (GPIODIR) Offset 0x400 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 DIR R/W 0 R/W 0 R/W 0 R/W 0 Bit 31:8 7:0 Name reserved DIR Type RO R/W Reset 0 0x00 Description Reserved bits return an indeterminate value, and should never be changed. GPIO Data Direction 0: Pins are inputs 1: Pins are outputs 101 Preliminary March 22, 2006 LM3S101 Data Sheet Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 The GPIOIS register is the interrupt sense register. Bits set to 1 in GPIOIS configure the corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. All bits are cleared by a reset. GPIO Interrupt Sense (GPIOIS) Offset 0x404 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 IS R/W 0 R/W 0 R/W 0 R/W 0 Bit 31:8 7:0 Name reserved IS Type RO R/W Reset 0 0x00 Description Reserved bits return an indeterminate value, and should never be changed. GPIO Interrupt Sense 0: Edge on corresponding pin is detected (edge-sensitive) 1: Level on corresponding pin is detected (level-sensitive) March 22, 2006 Preliminary 102 General-Purpose Input/Outputs (GPIOs) Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO Interrupt Sense (GPIOIS) register (see page 102) is set to detect edges, bits set to High in GPIOIBE configure the corresponding pin to detect both rising and falling edges, regardless of the corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 104). Clearing a bit configures the pin to be controlled by GPIOIEV. All bits are cleared by a reset. GPIO Interrupt Both Edges (GPIOIBE) Offset 0x408 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 IBE R/W 0 R/W 0 R/W 0 R/W 0 Bit 31:8 7:0 Name reserved IBE Type RO R/W Reset 0 0x00 Description Reserved bits return an indeterminate value, and should never be changed. GPIO Interrupt Both Edges 0: Interrupt generation is controlled by the GPIO Interrupt Event (GPIOIEV) register (see page 142). 1: Both edges on the corresponding pin trigger an interrupt. Note: Single edge is determined by the corresponding bit in GPIOIEV. 103 Preliminary March 22, 2006 LM3S101 Data Sheet Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C The GPIOIEV register is the interrupt event register. Bits set to High in GPIOIEV configure the corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in the GPIO Interrupt Sense (GPIOIS) register (see page 102). Clearing a bit configures the pin to detect falling edges or low levels, depending on the corresponding bit value in GPIOIS. All bits are cleared by a reset. GPIO Interrupt Event (GPIOIEV) Offset 0x40C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 IEV R/W 0 R/W 0 R/W 0 R/W 0 Bit 31:8 7:0 Name reserved IEV Type RO R/W Reset 0 0x00 Description Reserved bits return an indeterminate value, and should never be changed. GPIO Interrupt Event 0: Falling edge or Low levels on corresponding pins trigger interrupts. 1: Rising edge or High levels on corresponding pins trigger interrupts. March 22, 2006 Preliminary 104 General-Purpose Input/Outputs (GPIOs) Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the corresponding pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables interrupt triggering on that pin. All bits are cleared by a reset. GPIO Interrupt Mask (GPIOIM) Offset 0x410 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 IME R/W 0 R/W 0 R/W 0 R/W 0 Bit 31:8 7:0 Name reserved IME Type RO R/W Reset 0 0x00 Description Reserved bits return an indeterminate value, and should never be changed. GPIO Interrupt Mask Enable 0: Corresponding pin interrupt is masked. 1: Corresponding pin interrupt is not masked. 105 Preliminary March 22, 2006 LM3S101 Data Sheet Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 The GPIORIS register is the raw interrupt status register. Bits read High in GPIORIS reflect the status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the requirements have been met, before they are finally allowed to trigger by the GPIO Interrupt Mask (GPIOIM) register (see page 105). Bits read as zero indicate that corresponding input pins have not initiated an interrupt. All bits are cleared by a reset. GPIO Raw Interrupt Status (GPIORIS) Offset 0x414 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RIS RO 0 RO 0 RO 0 RO 0 Bit 31:8 7:0 Name reserved RIS Type RO RO Reset 0 0x00 Description Reserved bits return an indeterminate value, and should never be changed. GPIO Interrupt Raw Status Reflect the status of interrupt trigger condition detection on pins (raw, prior to masking). 0: Corresponding pin interrupt requirements not met. 1: Corresponding pin interrupt has met requirements. March 22, 2006 Preliminary 106 General-Purpose Input/Outputs (GPIOs) Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has been generated, or the interrupt is masked. GPIOMIS is the state of the interrupt after masking. GPIO Masked Interrupt Status (GPIOMIS) Offset 0x418 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 MIS RO 0 RO 0 RO 0 RO 0 Bit 31:8 7:0 Name reserved MIS Type RO RO Reset 0 0x00 Description Reserved bits return an indeterminate value, and should never be changed. GPIO Masked Interrupt Status Masked value of interrupt due to corresponding pin. 0: Corresponding GPIO line interrupt not active. 1: Corresponding GPIO line asserting interrupt. 107 Preliminary March 22, 2006 LM3S101 Data Sheet Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the corresponding interrupt edge detection logic register. Writing a 0 has no effect. GPIO Interrupt Clear (GPIOICR) Offset 0x41C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 W1C 0 W1C 0 W1C 0 W1C 0 IC W1C 0 W1C 0 W1C 0 W1C 0 Bit 31:8 7:0 Name reserved IC Type RO W1C Reset 0 0x00 Description Reserved bits return an indeterminate value, and should never be changed. GPIO Interrupt Clear 0: Corresponding interrupt is unaffected. 1: Corresponding interrupt is cleared. March 22, 2006 Preliminary 108 General-Purpose Input/Outputs (GPIOs) Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset, therefore no GPIO line is set to hardware control by default. Caution - All GPIO pins are inputs by default (GPIODIR=0 and GPIOAFSEL=0), with the exception of the five JTAG pins (PB7 and PC[3:0]). The JTAG pins default to their JTAG functionality (GPIOAFSEL=1). Asserting a Power-On-Reset (POR) or an external reset (RST) puts both groups of pins back to their default state. If the JTAG pins will be used as GPIOs in a design, PB7 and PC2 cannot have external pull-down resistors connected to both of them at the same time. If both pins are pulled Low during reset, the controller will have unpredictable behavior. If this happens, remove one or both of the pull-down resistors, and apply RST or power-cycle the part In addition, it is possible to create a software sequence that prevents the debugger from connecting to the Stellaris microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger will not have enough time to connect and halt the controller before the JTAG pin functionality switches. This locks the debugger out of the part. This can be avoided with a software routine that restores JTAG functionality using an external trigger.. GPIO Alternate Function Select (GPIOAFSEL) Offset 0x420 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W R/W R/W - AFSEL R/W R/W R/W R/W R/W - Bit 31:8 7:0 Name reserved AFSEL Type RO R/W Reset 0 see note Description Reserved bits return an indeterminate value, and should never be changed. GPIO Alternate Function Select 0: Software control of corresponding GPIO line (GPIO mode). 1: Hardware control of corresponding GPIO line (alternate hardware function). Note: The default reset value for the GPIOAFSEL register is 0x00 for all GPIO pins, with the exception of the five JTAG pins (PB7 and PC[3:0]). These five pins default to JTAG functionality. Because of this, the default reset value of GPIOAFSEL for GPIO Port B is 0x80 while the default reset value of GPIOAFSEL for Port C is 0x0F. 109 Preliminary March 22, 2006 LM3S101 Data Sheet Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing a DRV2 bit for a GPIO signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the GPIODR8R register are automatically cleared by hardware. GPIO 2-mA Drive Select (GPIODR2R) Offset 0x500 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 1 R/W 1 R/W 1 R/W 1 DRV2 R/W 1 R/W 1 R/W 1 R/W 1 Bit 31:8 7:0 Name reserved DRV2 Type RO R/W Reset 0 0xFF Description Reserved bits return an indeterminate value, and should never be changed. Output Pad 2-mA Drive Enable A write of 1 to either GPIODR4[n] or GPIODR8[n] clears the corresponding 2-mA enable bit. The change is effective on the second clock cycle after the write. March 22, 2006 Preliminary 110 General-Purpose Input/Outputs (GPIOs) Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 The GPIODR4R register is the 4-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing the DRV4 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV8 bit in the GPIODR8R register are automatically cleared by hardware. GPIO 4-mA Drive Select (GPIODR4R) Offset 0x504 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 DRV4 R/W 0 R/W 0 R/W 0 R/W 0 Bit 31:8 7:0 Name reserved DRV4 Type RO R/W Reset 0 0x00 Description Reserved bits return an indeterminate value, and should never be changed. Output Pad 4-mA Drive Enable A write of 1 to either GPIODR2[n] or GPIODR8[n] clears the corresponding 4-mA enable bit. The change is effective on the second clock cycle after the write. 111 Preliminary March 22, 2006 LM3S101 Data Sheet Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 The GPIODR8R register is the 8-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing the DRV8 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV4 bit in the GPIODR4R register are automatically cleared by hardware. GPIO 8-mA Drive Select (GPIODR8R) Offset 0x508 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 DRV8 R/W 0 R/W 0 R/W 0 R/W 0 Bit 31:8 7:0 Name reserved DRV8 Type RO R/W Reset 0 0x00 Description Reserved bits return an indeterminate value, and should never be changed. Output Pad 8-mA Drive Enable A write of 1 to either GPIODR2[n] or GPIODR4[n] clears the corresponding 8-mA enable bit. The change is effective on the second clock cycle after the write. March 22, 2006 Preliminary 112 General-Purpose Input/Outputs (GPIOs) Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C The GPIOODR register is the open drain control register. Setting a bit in this register enables the open drain configuration of the corresponding GPIO pad. When the open drain mode is enabled, the corresponding bit should also be set in the GPIO Digital Input Enable (GPIODEN) register (see page 117). Corresponding bits in the drive strength registers (GPIODR2R, GPIODR4R, GPIODR8R, and GPIOSLR) can be set to achieve the desired rise and fall times. The GPIO acts as an open drain input if the corresponding bit in the GPIODIR register is set to 0; and as an open drain output when set to 1. GPIO Open Drain Select (GPIOODR) Offset 0x50C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 ODE R/W 0 R/W 0 R/W 0 R/W 0 Bit 31:8 7:0 Name reserved ODE Type RO R/W Reset 0 0x00 Description Reserved bits return an indeterminate value, and should never be changed. Output Pad Open Drain Enable 0: Open drain configuration is disabled. 1: Open drain configuration is enabled. 113 Preliminary March 22, 2006 LM3S101 Data Sheet Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 The GPIOPUR register is the pull-up control register. When a bit is set to 1, it enables a weak pullup resistor on the corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 115). GPIO Pull-Up Select (GPIOPUR) Offset 0x510 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 1 R/W 1 R/W 1 R/W 1 PUE R/W 1 R/W 1 R/W 1 R/W 1 Bit 31:8 7:0 Name reserved PUE Type RO R/W Reset 0 0xFF Description Reserved bits return an indeterminate value, and should never be changed. Pad Weak Pull-Up Enable A write of 1 to GPIOPDR[n] clears the corresponding GPIOPUR[n] enables. The change is effective on the second clock cycle after the write. March 22, 2006 Preliminary 114 General-Purpose Input/Outputs (GPIOs) Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 The GPIOPDR register is the pull-down control register. When a bit is set to 1, it enables a weak pull-down resistor on the corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 114). GPIO Pull-Down Select (GPIOPDR) Offset 0x514 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 PDE R/W 0 R/W 0 R/W 0 R/W 0 Bit 31:8 7:0 Name reserved PDE Type RO R/W Reset 0 0x00 Description Reserved bits return an indeterminate value, and should never be changed. Pad Weak Pull-Down Enable A write of 1 to GPIOPUR[n] clears the corresponding GPIOPDR[n] enables. The change is effective on the second clock cycle after the write. 115 Preliminary March 22, 2006 LM3S101 Data Sheet Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 The GPIOSLR register is the slew rate control register. Slew rate control is only available when using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see page 112). GPIO Slew Rate Control Select (GPIOSLR) Offset 0x518 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 SRL R/W 0 R/W 0 R/W 0 R/W 0 Bit 31:8 7:0 Name reserved SRL Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. Slew Rate Limit Enable (8-mA drive only) 0: Slew rate control disabled. 1: Slew rate control enabled. March 22, 2006 Preliminary 116 General-Purpose Input/Outputs (GPIOs) Register 18: GPIO Digital Input Enable (GPIODEN), offset 0x51C The GPIODEN register is the digital input enable register. By default, all GPIO signals are configured as digital inputs at reset. The only time that a pin should not be configured as a digital input is when the GPIO pin is configured to be one of the analog input signals for the analog comparators. GPIO Digital Input Enable (GPIODEN) Offset 0x51C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 1 R/W 1 R/W 1 R/W 1 DEN R/W 1 R/W 1 R/W 1 R/W 1 Bit 31:8 7:0 Name reserved DEN Type RO R/W Reset 0 0xFF Description Reserved bits return an indeterminate value, and should never be changed. Digital-Input Enable 0: Digital Input disabled 1: Digital Input enabled 117 Preliminary March 22, 2006 LM3S101 Data Sheet Register 19: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 4 (GPIOPeriphID4) Offset 0xFD0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PID4 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 7:0 Name reserved PID4 Type RO RO Reset 0 0x00 Description Reserved bits return an indeterminate value, and should never be changed. GPIO Peripheral ID Register[7:0] March 22, 2006 Preliminary 118 General-Purpose Input/Outputs (GPIOs) Register 20: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 5 (GPIOPeriphID5) Offset 0xFD4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PID5 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 7:0 Name reserved PID5 Type RO RO Reset 0 0x00 Description Reserved bits return an indeterminate value, and should never be changed. GPIO Peripheral ID Register[15:8] 119 Preliminary March 22, 2006 LM3S101 Data Sheet Register 21: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 6 (GPIOPeriphID6) Offset 0xFD8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PID6 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 7:0 Name reserved PID6 Type RO RO Reset 0 0x00 Description Reserved bits return an indeterminate value, and should never be changed. GPIO Peripheral ID Register[23:16] March 22, 2006 Preliminary 120 General-Purpose Input/Outputs (GPIOs) Register 22: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 7 (GPIOPeriphID7) Offset 0xFDC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PID7 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 7:0 Name reserved PID7 Type RO RO Reset 0 0x00 Description Reserved bits return an indeterminate value, and should never be changed. GPIO Peripheral ID Register[31:24] 121 Preliminary March 22, 2006 LM3S101 Data Sheet Register 23: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 0 (GPIOPeriphID0) Offset 0xFE0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 PID0 RO 0 RO 0 RO 0 RO 1 Bit 31:8 7:0 Name reserved PID0 Type RO RO Reset 0 0x61 Description Reserved bits return an indeterminate value, and should never be changed. GPIO Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. March 22, 2006 Preliminary 122 General-Purpose Input/Outputs (GPIOs) Register 24: GPIO Peripheral Identification 1(GPIOPeriphID1), offset 0xFE4 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 1 (GPIOPeriphID1) Offset 0xFE4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PID1 RO 0 RO 0 RO 0 RO 0 Bit 31:8 7:0 Name reserved PID1 Type RO RO Reset 0 0x00 Description Reserved bits return an indeterminate value, and should never be changed. GPIO Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 123 Preliminary March 22, 2006 LM3S101 Data Sheet Register 25: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 2 (GPIOPeriphID2) Offset 0xFE8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 PID2 RO 1 RO 0 RO 0 RO 0 Bit 31:8 7:0 Name reserved PID2 Type RO RO Reset 0 0x18 Description Reserved bits return an indeterminate value, and should never be changed. GPIO Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. March 22, 2006 Preliminary 124 General-Purpose Input/Outputs (GPIOs) Register 26: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 3 (GPIOPeriphID3) Offset 0xFEC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PID3 RO 0 RO 0 RO 0 RO 1 Bit 31:8 7:0 Name reserved PID3 Type RO RO Reset 0 0x01 Description Reserved bits return an indeterminate value, and should never be changed. GPIO Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 125 Preliminary March 22, 2006 LM3S101 Data Sheet Register 27: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO Primecell Identification 0 (GPIOPCellID0) Offset 0xFF0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 CID0 RO 1 RO 1 RO 0 RO 1 Bit 31:8 7:0 Name reserved CID0 Type RO RO Reset 0 0x0D Description Reserved bits return an indeterminate value, and should never be changed. GPIO PrimeCell ID Register[7:0] Provides software a standard cross-peripheral identification system. March 22, 2006 Preliminary 126 General-Purpose Input/Outputs (GPIOs) Register 28: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO Primecell Identification 1 (GPIOPCellID1) Offset 0xFF4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1 CID1 RO 0 RO 0 RO 0 RO 0 Bit 31:8 7:0 Name reserved CID1 Type RO RO Reset 0 0xF0 Description Reserved bits return an indeterminate value, and should never be changed. GPIO PrimeCell ID Register[15:8] Provides software a standard cross-peripheral identification system. 127 Preliminary March 22, 2006 LM3S101 Data Sheet Register 29: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO Primecell Identification 2 (GPIOPCellID2) Offset 0xFF8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 CID2 RO 0 RO 1 RO 0 RO 1 Bit 31:8 7:0 Name reserved CID2 Type RO RO Reset 0 0x05 Description Reserved bits return an indeterminate value, and should never be changed. GPIO PrimeCell ID Register[23:16] Provides software a standard cross-peripheral identification system. March 22, 2006 Preliminary 128 General-Purpose Input/Outputs (GPIOs) Register 30: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO Primecell Identification 3 (GPIOPCellID3) Offset 0xFFC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 1 CID3 RO 0 RO 0 RO 0 RO 1 Bit 31:8 7:0 Name reserved CID3 Type RO RO Reset 0 0xB1 Description Reserved bits return an indeterminate value, and should never be changed. GPIO PrimeCell ID Register[31:24] Provides software a standard cross-peripheral identification system. 129 Preliminary March 22, 2006 LM3S101 Data Sheet 9 General-Purpose Timers Programmable timers can be used to count or time external events that drive the Timer input pins. The LM3S101 controller General-Purpose Timer Module (GPTM) contains two GPTM blocks (Timer0 and Timer1). Each GPTM block provides two 16-bit timer/counters (referred to as TimerA and TimerB) that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). The following modes are supported: 32-bit Timer modes: - Programmable one-shot timer - Programmable periodic timer - Real-Time Clock using 32-KHz input clock - Software-controlled event stalling (excluding RTC mode) 16-bit Timer modes: - General-purpose timer function with an 8-bit prescaler - Programmable one-shot timer - Programmable periodic timer - Software-controlled event stalling 16-bit Input Capture modes: - Input edge count capture - Input edge time capture 16-bit PWM mode: - Simple PWM mode with software-programmable output inversion of the PWM signal March 22, 2006 Preliminary 130 General-Purpose Timers 9.1 Figure 9-1. Block Diagram GPTM Block Diagram 0x0000 (Down Counter Modes ) Timer A Control GPTMTAPMR GPTMTAPR GPTMTAMATCHR Interrupt/Config Timer A Interrupt GPTMCFG GPTMCTL GPTMIMR Timer B Interrupt GPTMRIS GPTMMIS GPTMICR Timer B Control GPTMTBPMR GPTMTBPR GPTMTBMATCHR GPTMTBILR GPTMTBMR TB Comparator GPTMTBR En Clk/Edge Detect CCP1 RTC Divider GPTMTAILR GPTMTAMR GPTMAR En Clk/Edge Detect 32KHz TA Comparator 0x0000 (Down Counter Modes ) System Clock 9.2 Functional Description The main components of each GPTM block are two free-running 16-bit up/down counters (referred to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two 16bit load/ initialization registers and their associated control functions. The exact functionality of each GPTM is controlled by software and configured through the register interface. Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 141), the TimerA Mode (GPTMTAMR) register (see page 142), and the TimerB Mode (GPTMTBMR) register (see page 143). When in one of the 32-bit modes, the timer can only act as a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers configured in any combination of the 16-bit modes. 9.2.1 GPTM Reset Conditions After reset has been applied to the GPTM module, the module is in an inactive state, and all control registers are cleared and in their default states. Counters TimerA and TimerB are initialized to 0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load (GPTMTAILR) register (see page 150) and the GPTM TimerB Interval Load (GPTMTBILR) register (see page 151). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale (GPTMTAPR) register (see page 154) and the GPTM TimerB Prescale (GPTMTBPR) register (see page 155). 131 Preliminary March 22, 2006 LM3S101 Data Sheet 9.2.2 32-Bit Timer Operating Modes Note: The odd-numbered CCP pins are used for 16-bit input and the even-numbered CCP pins are used for 32-bit input. This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their configuration. The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1 (RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTM registers are concatenated to form pseudo 32-bit registers. These registers include: GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 150 GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 151 GPTM TimerA (GPTMTAR) register [15:0], see page 158 GPTM TimerB (GPTMTBR) register [15:0], see page 159 In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is: GPTMTBILR[15:0]:GPTMTAILR[15:0]. Likewise, a read access to GPTMTAR returns the value: GPTMTBR[15:0]:GPTMTAR[15:0]. 9.2.2.1 32-Bit One-Shot/Periodic Timer Mode In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is determined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR) register (see page 142), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR) register. When software writes the TAEN bit in the GPTM Control (GPTMCTL) register (see page 144), the timer begins counting down from its preloaded value. Once the 0x00000000 state is reached, the timer reloads its start value from the concatenated GPTMTAILR on the next cycle. If configured to be a one-shot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. If configured as a periodic timer, it continues counting. In addition to reloading the count value, the GPTM generates interrupts and output triggers when it reaches the 0x0000000 state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register (see page 147), and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register (see page 149). If the time-out interrupt is enabled in the GPTM Interrupt Mask (GPTIMR) register (see page 146), the GPTM also sets the TATOMIS bit in the GPTM Masked Interrupt Status (GPTMISR) register (see page 148). The output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x00000000 state, and deasserted on the following clock cycle. It is enabled by setting the TAOTE bit in GPTMCTL. If software reloads the GPTMTAILR register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. If the TASTALL bit in the GPTMCTL register is asserted, the timer freezes counting until the signal is deasserted. 9.2.2.2 32-Bit Real-Time Clock Timer Mode In Real-Time Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registers are configured as a 32-bit up-counter. When RTC mode is selected for the first time, the counter is loaded with a value of 0x00000001. All subsequent load values must be written to the GPTM TimerA Match (GPTMTAMATCHR) register (see page 152) by the controller. March 22, 2006 Preliminary 132 General-Purpose Timers The 32KHZ pin is dedicated to the 32-bit RTC function, and the input clock is 32 KHz. When software writes the TAEN bit in GPTMCTL, the counter starts counting up from its preloaded value of 0x00000001. When the current count value matches the preloaded value in GPTMTAMATCHR, it rolls over to a value of 0x00000000 and continues counting until either a hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs, the GPTM asserts the RTCRIS bit in GPTMRIS. If the RTC interrupt is enabled in GPTIMR, the GPTM also sets the RTCMIS bit in GPTMISR and generates a controller interrupt. The status flags are cleared by writing the RTCCINT bit in GPTMICR. If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if the RTCEN bit is set in GPTMCTL. 9.2.3 16-Bit Timer Operating Modes The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the GPTM Configuration (GPTMCFG) register (see page 141). This section describes each of the GPTM 16-bit modes of operation. Timer A and Timer B have identical modes, so a single description is given using an n to reference both. 9.2.3.1 16-Bit One-Shot/Periodic Timer Mode In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. The selection of one-shot or periodic mode is determined by the value written to the TnMR field of the GPTMTnMR register. The optional prescaler is loaded into the Timern Prescale (GPTMTnPR) register. When software writes the TnEN bit in the GPTMCTL register, the timer begins counting down from its preloaded value. Once the 0x0000 state is reached, the timer reloads its start value from GPTMTnILR and GPTMTnPR on the next cycle. If configured to be a one-shot timer, the timer stops counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, it continues counting. In addition to reloading the count value, the timer generates interrupts and output triggers when it reaches the 0x0000 state. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it until it is cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTIMR, the GPTM also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt. The output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x0000 state, and deasserted on the following clock cycle. It is enabled by setting the TnOTE bit in the GPTMCTL register, and can trigger SoC-level events. If software reloads the GPTMTAILR register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. If the TnSTALL bit in the GPTMCTL register is enabled, the timer freezes counting until the signal is deasserted. The following example shows a variety of configurations for a 16-bit free running timer while using the prescaler. All values assume a 50 MHz clock with Tc=20 ns (clock period). Table 9-1. Prescale 00000000 00000001 1 2 16-Bit Timer With Prescaler Configurations #Clock (Tc)a Max Time 1.3107 2.6214 Units mS mS 133 Preliminary March 22, 2006 LM3S101 Data Sheet Table 9-1. Prescale 00000010 -----------11111100 11111110 11111111 16-Bit Timer With Prescaler Configurations #Clock (Tc)a 3 -254 255 256 332.9229 334.2336 335.5443 mS mS mS Max Time 3.9321 Units mS a. Tc is the clock period. 9.2.3.2 16-Bit Input Edge Count Mode In Edge Count mode, the timer is configured as a down-counter capable of capturing three types of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined by the TnEVENT fields of the GPTMCTL register. During initialization, the Timern Match (GPTMTnMATCHR) register is configured so that the difference between the value in the GPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events that must be counted. When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit (and the CnMMIS bit, if the interrupt is not masked). The counter is then reloaded using the value in GPTMTnILR, and stopped since the GPTM automatically clears the TnEN bit in the GPTMCTL register. Once the event count has been reached, all further events are ignored until TnEN is reenabled by software. Figure 9-2 shows how input edge count mode works. In this case, the timer start value is set to GPTMnILR=0x000A and the match value is set to GPTMnMATCHR=0x0006 so that 4 edge events are counted. The counter is configured to detect both edges of the input signal. Note that the last two edges are not counted since the timer automatically clears the TnEN bit after the current count matches the value in the GPTMnMR register. March 22, 2006 Preliminary 134 General-Purpose Timers Figure 9-2. 16-Bit Input Edge Count Mode Example Timer reload on next cycle Ignored Ignored Count 0x000A 0x0009 0x0008 0x0007 0x0006 Timer stops, flags asserted Input Signal 9.2.3.3 16-Bit Input Edge Time Mode In Edge Time mode, the timer is configured as a free running down-counter initialized to the value loaded in the GPTMTnILR register (or 0xFFFF at reset). This mode allows for event capture of both rising and falling edges. The timer is placed into Edge Time mode by setting the TnCMR bit in the GPTMTnMR register, and the type of event that the timer captures is determined by the TnEVENT fields of the GPTMCTL register. When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture. When the selected input event is detected, the current Tn counter value is captured in the GPTMTnR register and is available to be read by the controller. The GPTM then asserts the CnERIS bit (and the CnEMIS bit, if the interrupt is not masked). After an event has been captured, the timer does not stop counting. It continues to count until the TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the GPTMnILR register. Figure 9-3 shows how input edge timing mode works. In the diagram, it is assumed that the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture rising edge events. Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR register, and is held there until another rising edge is detected (at which point the new count value is loaded into GPTMTnR). 135 Preliminary March 22, 2006 LM3S101 Data Sheet Figure 9-3. 16-Bit Input Edge Time Mode Example Count GPTMTnR=X GPTMTnR=Y GPTMTnR=Z 0xFFFF Z X Y Time Input Signal 9.2.3.4 16-Bit PWM Mode The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a down-counter with a start value (and thus period) defined by GPTMTnILR. PWM mode is enabled by setting the TnAMS bit in the GPTMTnMR register. PWM mode can take advantage of the 8-bit prescaler by using the Timern Prescale Register (GPTMTnPR) and the Timern Prescale Match Register (GPTMTnPMR). This effectively extends the range of the timer to 24 bits. When software writes the GPTMCTL register TnEN bit, the counter begins counting down until it reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from GPTMTnILR (and GPTMTnPR if using a prescaler) and continues counting until disabled by software clearing the TnEN bit in the GPTMCTL register. No interrupts or status bits are asserted in PWM mode. The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its start state), and is deasserted when the counter value equals the value in the Timern Match Register (GPTMnMATCHR). Software has the capability of inverting the output PWM signal by setting the TnPWML bit in the GPTMCTL register. Figure 9-4 shows how to generate an output PWM with a 1-ms period and a 66% duty cycle assuming a 50 MHz input clock and TnPWML=0 (duty cycle would be 33% for the TnPWML=1 configuration). For this example, the start value is GPTMnIRL=0xC350 and the match value is GPTMnMR=0x411A. March 22, 2006 Preliminary 136 General-Purpose Timers Figure 9-4. 16-Bit PWM Mode Example Count GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR 0xC350 0x411A Time TnEN set TnPWML = 0 Output Signal TnPWML = 1 9.3 Initialization and Configuration This section shows module initialization and configuration examples for each of the supported timer modes. 9.3.1 32-bit One-Shot/Periodic Timer Mode The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence: 1. Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making any changes. 2. Write the Configuration Register (GPTMCFG) to a value of 0x0. 3. Set the TAMR field in the TimerA Mode Register (GPTMTAMR): a. Write a value of 0x1 for One-Shot mode. b. Write a value of 0x2 for Periodic mode. 4. Load the start value into the TimerA Interval Load Register (GPTMTAILR). 5. If interrupts are required, set the TATOIM bit in the Interrupt Mask Register (GPTMIMR). 6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting. 7. Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the Interrupt Clear Register (GPTMICR). In One-Shot mode, the timer stops counting after step 7. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out. 137 Preliminary March 22, 2006 LM3S101 Data Sheet 9.3.2 32-Bit Real-Time Clock (RTC) Mode To use the RTC mode, the timer must have a 32-KHz input signal on its 32KHz pin. To enable the RTC feature, follow these steps: 1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes. 2. Write the Configuration Register (GPTMCFG) with a value of 0x1. 3. Write the desired match value to the TimerA Match Register (GPTMTAMATCHR). 4. Set/clear the RTCEN bit in the Control Register (GPTMCTL) as desired. 5. If interrupts are required, set the RTCIM bit in the Interrupt Mask Register (GPTMIMR). 6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting. When the timer count equals the value in the GPTMTAMATCHR register, the counter is re-loaded with 0x00000000 and begins counting. If an interrupt is enabled, it does not have to be cleared. 9.3.3 16-Bit One-Shot/Periodic Timer Mode A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence: 1. Ensure the target timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the Configuration Register (GPTMCFG) to a value of 0x4. 3. Set the TnMR field in the Timer Mode (GPTMTnMR) register: a. Write a value of 0x1 for One-Shot mode. b. Write a value of 0x2 for Periodic mode. 4. If a prescaler is to be used, write the prescale value to the Timern Prescale Register (GPTMTnPR). 5. Load the start value into the Timer Interval Load Register (GPTMTnILR). 6. If interrupts are required, set the TnTOIM bit in the Interrupt Mask Register (GPTMIMR). 7. Set the TnEN bit in the Control Register (GPTMCTL) to enable the timer and start counting. 8. Poll the TnTORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the TnTOCINT bit of the Interrupt Clear Register (GPTMICR). In One-Shot mode, the timer stops counting after step 8. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out. 9.3.4 16-Bit Input Edge Count Mode A timer is configured to Input Edge Count mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register to a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR field to 0x3. 4. Configure the type of event(s) that the timer will capture by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the Timern Interval Load (GPTMTnILR) register. 6. Load the desired event count into the Timern Match (GPTMTnMATCHR) register. 7. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register. March 22, 2006 Preliminary 138 General-Purpose Timers 8. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events. 9. Poll the CnMRIS bit or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the Interrupt Clear (GPTMICR) register. In Input Edge Count Mode, the timer stops after the desired number of edge events has been detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat steps 4-9. 9.3.5 16-Bit Input Edge Timing Mode A timer is configured to Input Edge Timing mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register to a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR field to 0x3. 4. Configure the type of event that the timer will capture by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the Timern Interval Load (GPTMTnILR) register. 6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting. 8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained by reading the GPTM Timern (GPTMTnR) register. In Input Edge Timing mode, the timer continues running after an edge event has been detected, but the timer interval can be changed at any time by writing the GPTMTnILR register. The change takes effect at the next cycle after the write. 9.3.6 16-Bit PWM Mode A timer is configured to PWM mode using the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register to a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS field to 0x1 and the TnMR field to 0x2. 4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the Timern Interval Load (GPTMTnILR) register. 6. Load the Timern Match (GPTMTnMATCHR) register with the desired value. 7. If a prescaler is going to be used, configure the Timern Prescale (GPTMTnPR) register and the Timern Prescale Match (GPTMTnPMR) register. 8. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin generation of the output PWM signal. 139 Preliminary March 22, 2006 LM3S101 Data Sheet In PWM Timing mode, the timer continues running after the PWM signal has been generated. The PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes effect at the next cycle after the write. 9.4 Register Map Table 9-1 lists the GPTM registers. All addresses given are relative to that timer's base address: Timer0: 0x40030000 Timer1: 0x40031000 Table 9-2. Offset 0x000 0x004 0x008 0x00C 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x040 0x044 0x048 0x04C GPTM Register Map Name GPTMCFG GPTMTAMR GPTMTBMR GPTMCTL GPTMIMR GPTMRIS GPTMMIS GPTMICR GPTMTAILR GPTMTBILR GPTMTAMATCHR GPTMTBMATCHR GPTMTAPR GPTMTBPR GPTMTAPMR GPTMTBPMR GPTMTAR GPTMTBR Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x0000FFFF 0x0000FFFF 0x00000000 0x00000000 0x00000000 0x00000000 0xFFFFFFFF 0x0000FFFF Type R/W R/W R/W R/W R/W RO RO W1C R/W R/W R/W R/W R/W R/W R/W R/W RO RO Description Configuration reset value TimerA mode reset value TimerB mode reset value Control reset value Interrupt mask reset value Interrupt status reset value Masked interrupt status reset value Interrupt clear reset value TimerA interval load reset value TimerB interval load reset value TimerA match reset value TimerB match reset value TimerA prescale reset value TimerB prescale reset value TimerA prescale match reset value TimerB prescale match reset value TimerA reset value TimerB reset value See page 141 142 143 144 146 147 148 149 150 151 152 153 154 155 156 157 158 159 9.5 Register Descriptions The remainder of this section lists and describes the GPTM registers, in numerical order by address offset. March 22, 2006 Preliminary 140 General-Purpose Timers Register 1: GPTM Configuration (GPTMCFG), offset 0x000 This register configures the global operation of the GPTM module. The value written to this register determines whether the GPTM is in 32- or 16-bit mode. GPTM Configuration (GPTMCFG) Offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 GPTMCFG R/W 0 R/W 0 Bit 31:3 2:0 Name reserved GPTMCFG Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. GPTM Configuration 0x0: 32-bit timer configuration. 0x1: 32-bit real-time clock (RTC) counter configuration. 0x2: Reserved. 0x3: Reserved. 0x4-0x7: 16-bit timer configuration, function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR. 141 Preliminary March 22, 2006 LM3S101 Data Sheet Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 This register configures the GPTM based on the configuration selected in the GPTMCFG. When in 16-bit PWM mode, the TATMR field should be set to 0x3, and the TACMR should be set to 0x0. GPTM TimerA Mode (GPTMTAMR) Offset 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 TAAMS TACMR R/W 0 R/W 0 R/W 0 TAMR R/W 0 Bit 31:4 3 Name reserved TAAMS Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. GPTM TimerA Alternate Mode Select 0: Capture mode is enabled. 1: PWM mode is enabled. 2 TACMR R/W 0 GPTM TimerA Capture Mode 0: Edge-Count mode. 1: Edge-Time mode. 1:0 TAMR R/W 0 GPTM TimerA Mode 0x0: Reserved. 0x1: One-Shot Timer mode. 0x2: Periodic Timer mode. 0x3: Capture mode. The Timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register (16-or 32-bit). In 16-bit timer configuration, these bits control the 16-bit timer modes for TimerA. In 32-bit timer configuration, this register controls the mode and the contents of GPTMTBMR are ignored. March 22, 2006 Preliminary 142 General-Purpose Timers Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 This register configures the GPTM based on the configuration selected in GPTMCFG. When in 16bit PWM mode, the TBTMR field should be set to 0x3, and the TBCMR should be set to 0x0. GPTM TimerB Mode (GPTMTBMR) Offset 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 TBAMS TBCMR R/W 0 R/W 0 R/W 0 TBMR R/W 0 Bit 31:4 3 Name reserved TBAMS Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. GPTM TimerB Alternate Mode Select 0: Capture mode is enabled. 1: PWM mode is enabled. 2 TBCMR R/W 0 GPTM TimerB Capture Mode 0: Edge-Count mode. 1: Edge-Time mode. 1:0 TBMR R/W 0 GPTM TimerB Mode 0x0: Reserved. 0x1: One-Shot Timer mode. 0x2: Periodic Timer mode. 0x3: Capture mode. The timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register. In 16-bit timer configuration, these bits control the 16-bit timer modes for TimerB. In 32-bit timer configuration, this register's contents are ignored and GPTMTAMR is used. 143 Preliminary March 22, 2006 LM3S101 Data Sheet Register 4: GPTM Control (GPTMCTL), offset 0x00C This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer configuration, and to enable other features such as timer stall and the output trigger. GPTM Control (GPTMCTL) Offset 0x00C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 res Type Reset RO 0 TBPWML R/W 0 TBOTE R/W 0 res RO 0 TBEVENT R/W 0 R/W 0 TBSTALL R/W 0 TBEN R/W 0 res RO 0 TAPWML TAOTE R/W 0 R/W 0 RTCEN R/W 0 TAEVENT R/W 0 R/W 0 TASTALL R/W 0 TAEN R/W 0 Bit 31:15 14 Name reserved TBPWML Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. GPTM TimerB PWM Output Level 0: Output is unaffected. 1: Output is inverted. 13 TBOTE R/W 0 GPTM TimerB Output Trigger Enable 0: The output TimerB trigger is disabled. 1: The output TimerB trigger is enabled. 12 11:10 reserved TBEVENT RO R/W 0 0 Read as 0. GPTM TimerB Event Mode 00: Positive Edge. 01: Negative Edge. 11: Both Edges. 9 TBSTALL R/W 0 GPTM TimerB Stall Enable 0: TimerB stalling is disabled. 1: TimerB stalling is enabled. 8 TBEN R/W 0 GPTM TimerB Enable 0: TimerB is disabled. 1: TimerB is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. 7 6 reserved TAPWML RO R/W 0 0 Read as 0. GPTM TimerA PWM Output Level 0: Output is unaffected. 1: Output is inverted. March 22, 2006 Preliminary 144 General-Purpose Timers Bit 5 Name TAOTE Type R/W Reset 0 Description GPTM TimerA Output Trigger Enable 0: The output TimerA trigger is disabled. 1: The output TimerA trigger is enabled. 4 RTCEN R/W 0 GPTM RTC Enable 0: RTC counting is disabled 1: RTC counting is enabled 3:2 TAEVENT R/W 0 GPTM TimerA Event Mode 00: Positive edge. 01: Negative edge. 11: Both edges. 1 TASTALL R/W 0 GPTM TimerA Stall Enable 0: TimerA stalling is disabled. 1: TimerA stalling is enabled. 0 TAEN R/W 0 GPTM TimerA Enable 0: TimerA is disabled. 1: TimerA is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. 145 Preliminary March 22, 2006 LM3S101 Data Sheet Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1 enables the interrupt, while writing a 0 disables it. GPTM Interrupt Mask (GPTMIMR) Offset 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 C2EIM C2MIM TBTOIM R/W 0 R/W 0 R/W 0 RO 0 reserved RO 0 RO 0 RO 0 RTCIM R/W 0 C1EIM C1MIM TATOIM R/W 0 R/W 0 R/W 0 Bit 31:11 10 Name reserved C2EIM Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. GPTM Capture2 Event Interrupt Mask 0: Interrupt is disabled. 1: Interrupt is enabled. 9 C2MIM R/W 0 GPTM Capture2 Match Interrupt Mask 0: Interrupt is disabled. 1: Interrupt is enabled. 8 TBTOIM R/W 0 GPTM TimerB Time-Out Interrupt Mask 0: Interrupt is disabled. 1: Interrupt is enabled. 7:4 3 reserved RTCIM RO R/W 0 0 Read as 0. GPTM RTC Interrupt Mask 0: Interrupt is disabled. 1: Interrupt is enabled. 2 C1EIM R/W 0 GPTM Capture1 Event Interrupt Mask 0: Interrupt is disabled. 1: Interrupt is enabled. 1 C1MIM R/W 0 GPTM Capture1 Match Interrupt Mask 0: Interrupt is disabled. 1: Interrupt is enabled. 0 TATOIM R/W 0 GPTM TimerA Time-Out Interrupt Mask 0: Interrupt is disabled. 1: Interrupt is enabled. March 22, 2006 Preliminary 146 General-Purpose Timers Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its corresponding bit in GPTMICR. 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Offset 0x01C 31 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 C2ERIS RO 0 C2MRIS TBTORIS RO 0 RO 0 RO 0 reserved RO 0 RO 0 RO 0 RTCRIS RO 0 C1ERIS RO 0 C1MRIS TATORIS RO 0 RO 0 Bit 31:11 10 Name reserved C2ERIS Type RO RO Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. GPTM Capture2 Event Raw Interrupt This is the Capture2 Event interrupt status prior to masking. 9 C2MRIS RO 0 GPTM Capture2 Match Raw Interrupt This is the Capture2 Match interrupt status prior to masking. 8 TBTORIS RO 0 GPTM TimerB Time-Out Raw Interrupt This is the TimerB time-out interrupt status prior to masking. 7:4 3 reserved RTCRIS RO RO 0 0 Read as 0. GPTM RTC Raw Interrupt This is the RTC Event interrupt status prior to masking. 2 C1ERIS RO 0 GPTM Capture1 Event Raw Interrupt This is the Capture1 Event interrupt status prior to masking. 1 C1MRIS RO 0 GPTM Capture1 Match Raw Interrupt This is the Capture1 Match interrupt status prior to masking. 0 TATORIS RO 0 GPTM TimerA Time-Out Raw Interrupt This the TimerA time-out interrupt status prior to masking. 147 Preliminary March 22, 2006 LM3S101 Data Sheet Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR. GPTM Masked Interrupt Status (GPTMMIS) Offset 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 C2EMIS C2MMISTBTOMIS RO 0 RO 0 RO 0 RO 0 reserved RO 0 RO 0 RO 0 RTCMIS C1EMIS C1MMISTATOMIS RO 0 RO 0 RO 0 RO 0 Bit 31:11 10 Name reserved C2EMIS Type RO RO Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. GPTM Capture2 Event Masked Interrupt This is the Capture2 Event interrupt status after masking. 9 C2MMIS RO 0 GPTM Capture2 Match Masked Interrupt This is the Capture2 Match interrupt status after masking. 8 TBTOMIS RO 0 GPTM TimerB Time-Out Masked Interrupt This is the TimerB time-out interrupt status after masking. 7:4 3 reserved RTCMIS RO RO 0 0 Read as 0s. GPTM RTC Masked Interrupt This is the RTC Event interrupt status after masking. 2 C1EMIS RO 0 GPTM Capture1 Event Masked Interrupt This is the Capture1 Event interrupt status after masking. 1 C1MMIS RO 0 GPTM Capture1 Match Masked Interrupt This is the Capture1 Match interrupt status after masking. 0 TATOMIS RO 0 GPTM TimerA Time-Out Masked Interrupt This is the TimerA time-out interrupt status after masking. March 22, 2006 Preliminary 148 General-Purpose Timers Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1 to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers. GPTM Interrupt Clear (GPTMICR) Offset 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RTCCINT C2ECINT C2MCINT TBTOCINT W1C 0 W1C 0 W1C 0 W1C 0 RO 0 RO 0 reserved RO 0 RO 0 RO 0 C1ECINT C1MCINT TATOCINT W1C 0 W1C 0 W1C 0 Bit 31:11 10 Name reserved C2ECINT Type RO W1C Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. GPTM Capture2 Event Interrupt Clear 0: The interrupt is unaffected. 1: The interrupt is cleared. 9 C2MCINT W1C 0 GPTM Capture2 Match Interrupt Clear 0: The interrupt is unaffected. 1: The interrupt is cleared. 8 TBTOCINT W1C 0 GPTM TimerB Time-Out Interrupt Clear 0: The interrupt is unaffected. 1: The interrupt is cleared. 7:4 3 reserved RTCCINT RO W1C 0 0 Reserved bits return an indeterminate value, and should never be changed. GPTM RTC Interrupt Clear 0: The interrupt is unaffected. 1: The interrupt is cleared. 2 C1ECINT W1C 0 GPTM Capture1 Event Interrupt Clear 0: The interrupt is unaffected. 1: The interrupt is cleared. 1 C1MCINT W1C 0 GPTM Capture1 Match Raw Interrupt This is the Capture1 Match interrupt status after masking. 0 TATOCINT W1C 0 GPTM TimerA Time-Out Raw Interrupt 0: The interrupt is unaffected. 1: The interrupt is cleared. 149 Preliminary March 22, 2006 LM3S101 Data Sheet Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 This register is used to load the starting count value into the timer. When GPTM is configured to one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond to the contents of the TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the upper 16 bits of this register read as 0's and have no effect on the state of GPTMTBILR. GPTM TimerA Interval Load (GPTMTAILR) Offset 0x028 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TAILRH Type Reset R/W 1/0 15 R/W 1/0 14 R/W 1/0 13 R/W 1/0 12 R/W 1/0 11 R/W 1/0 10 R/W 1/0 9 R/W 1/0 8 R/W 1/0 7 R/W 1/0 6 R/W 1/0 5 R/W 1/0 4 R/W 1/0 3 R/W 1/0 2 R/W 1/0 1 R/W 1/0 0 TAILRL Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 1/0 = 1 if timer is configured in 32-bit mode; 0 if timer is configured in 16-bit mode. Bit 31:16 Name TAILRH Type R/W Reset 0xFFFF (32-bit mode) 0x0000 (16-bit mode) Description GPTM TimerA Interval Load Register High When configured for 32-bit mode via the GPTMCFG register, the TimerB Interval Load (GPTMTBILR) register loads this value on a write. A read returns the current value of GPTMTBILR. In 16-bit mode, this field reads as 0 and does not have an effect on the state of GPTMTBILR. GPTM TimerA Interval Load Register Low For both 16- and 32-bit modes, writing this field loads the counter for TimerA. A read returns the current value of GPTMTAILR. 15:0 TAILRL R/W 0xFFFF March 22, 2006 Preliminary 150 General-Purpose Timers Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C This register is used to load the starting count value into TimerB. When the GPTM is configured to a 32-bit mode, GPTMTBILR returns the current value of TimerB and ignores writes. GPTM TimerB Interval Load (GPTMTBILR) Offset 0x02C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 TBILRL Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit 31:16 15:0 Name reserved TBILRL Type RO R/W Reset 0 0xFFFF Description Reserved bits return an indeterminate value, and should never be changed. GPTM TimerB Interval Load Register When the GPTM is not configured as a 32-bit timer, a write to this field updates GPTMTBILR. In 32-bit mode, writes are ignored, and reads return the current value of GPTMTBILR. 151 Preliminary March 22, 2006 LM3S101 Data Sheet Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes. GPTM TimerA Match (GPTMTAMATCHR) Offset 0x030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TAMRH Type Reset R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 R/W 0 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 TAMRL Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit 31:16 Name TAMRH Type R/W Reset 0xFFFF (32-bit mode) 0x0000 (16-bit mode) Description GPTM TimerA Match Register High When configured for 32-bit Real-Time Clock (RTC) mode via the GPTMCFG register, this value is compared to the upper half of GPTMTAR, to determine match events. In 16-bit mode, this field reads as 0 and does not have an effect on the state of GPTMTBMATCHR. GPTM TimerA Match Register Low When configured for 32-bit Real-Time Clock (RTC) mode via the GPTMCFG register, this value is compared to the lower half of GPTMTAR, to determine match events. When configured for PWM mode, this this value along with GPTMTAILR, determines the duty cycle of the output PWM signal. When configured for Edge Count mode, this value along with GPTMTAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTAILR minus this value. 15:0 TAMRL R/W 0xFFFF March 22, 2006 Preliminary 152 General-Purpose Timers Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes. GPTM TimerB Match (GPTMTBMATCHR) Offset 0x034 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 TBMRL Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit 31:16 15:0 Name reserved TBMRL Type RO R/W Reset 0 0xFFFF Description Reserved bits return an indeterminate value, and should never be changed. GPTM TimerB Match Register Low When configured for PWM mode, this value along with GPTMTBILR, determines the duty cycle of the output PWM signal. When configured for Edge Count mode, this value along with GPTMTBILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTBILR minus this value. 153 Preliminary March 22, 2006 LM3S101 Data Sheet Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 This register allows software to extend the range of the 16-bit timers. GPTM TimerA Prescale (GPTMTAPR) Offset 0x038 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 TAPSR R/W 0 R/W 0 R/W 0 R/W 0 Bit 31:8 7:0 Name reserved TAPSR Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. GPTM TimerA Prescale The register loads this value on a write. A read returns the current value of the register. Refer to Table 9-1 on page 133 for more details and an example. March 22, 2006 Preliminary 154 General-Purpose Timers Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C This register allows software to extend the range of the 16-bit timers. GPTM TimerB Prescale (GPTMTBPR) Offset 0x03C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 TBPSR R/W 0 R/W 0 R/W 0 R/W 0 Bit 31:8 7:0 Name reserved TBPSR Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. GPTM TimerB Prescale The register loads this value on a write. A read returns the current value of this register. Refer to Table 9-1 on page 133 for more details and an example. 155 Preliminary March 22, 2006 LM3S101 Data Sheet Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 This register effectively extends the range of GPTMTAMATCHR to 24 bits. GPTM TimerA Prescale Match (GPTMTAPMR) Offset 0x040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 TAPSMR R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit 31:8 7:0 Name reserved TAPSMR Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. GPTM TimerA Prescale Match This value is used alongside GPTMTAMATCHR to detect timer match events while using a prescaler. March 22, 2006 Preliminary 156 General-Purpose Timers Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 This register effectively extends the range of GPTMTBMATCHR to 24 bits. GPTM TimerB Prescale Match (GPTMTBPMR) Offset 0x044 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 TBPSMR R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit 31:8 7:0 Name reserved TBPSMR Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. GPTM TimerB Prescale Match This value is used alongside GPTMTBMATCHR to detect timer match events while using a prescaler. 157 Preliminary March 22, 2006 LM3S101 Data Sheet Register 17: GPTM TimerA (GPTMTAR), offset 0x048 This register shows the current value of the TimerA counter in all cases except for Input Edge Count mode. When in this mode, this register contains the time at which the last edge event took place. GPTM TimerA (GPTMTAR) Offset 0x048 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TARH Type Reset RO 1/0 15 RO 1/0 14 RO 1/0 13 RO 1/0 12 RO 1/0 11 RO 1/0 10 RO 1/0 9 RO 1/0 8 RO 1/0 7 RO 1/0 6 RO 1/0 5 RO 1/0 4 RO 1/0 3 RO 1/0 2 RO 1/0 1 RO 1/0 0 TARL Type Reset RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 1/0 = 1 if timer is configured in 32-bit mode; 0 if timer is configured in 16-bit mode. Bit 31:16 Name TARH Type RO Reset 0xFFFF (32-bit mode) 0x0000 (16-bit mode) Description GPTM TimerA Register High If the GPTMCFG is in a 32-bit mode, TimerB value is read. If the GPTMCFG is in a 16-bit mode, this is read as zero. 15:0 TARL RO 0xFFFF GPTM TimerA Register Low A read returns the current value of the TimerA Count Register, except in Input Edge Count mode, when it returns the timestamp from the last edge event. March 22, 2006 Preliminary 158 General-Purpose Timers Register 18: GPTM TimerB (GPTMTBR), offset 0x04C This register shows the current value of the TimerB counter in all cases except for Input Edge Count mode. When in this mode, this register contains the time at which the last edge event took place. GPTM TimerB (GPTMTBR) Offset 0x04C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 TBRL Type Reset RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 Bit 31:16 15:0 Name reserved TBRL Type RO RO Reset 0 0xFFFF Description Reserved bits return an indeterminate value, and should never be changed. GPTM TimerB A read returns the current value of the TimerB Count Register, except in Input Edge Count mode, when it returns the timestamp from the last edge event. 159 Preliminary March 22, 2006 LM3S101 Data Sheet 10 Watchdog Timer A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. The LM3S101 controller Watchdog Timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, and a locking register. The Watchdog Timer can be configured to generate an interrupt to the controller on its first timeout, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. 10.1 Block Diagram Watchdog Timer Block Diagram Control / Clock / Interrupt Generation WDTCTL WDTICR Interrupt WDTRIS WDTMIS WDTLOCK System Clock Comparator WDTVALUE 32-bit Down Counter 0x00000000 WDTLOAD Figure 10-1. Prime Cell WDTPCellID0 WDTPCellID1 WDTPCellID2 WDTPCellID3 Peripheral ID WDTPeriphID0 WDTPeriphID1 WDTPeriphID2 WDTPeriphID3 WDT PeriphID4 WDTPeriphID5 WDTPeriphID6 WDTPeriphID7 March 22, 2006 Preliminary 160 Watchdog Timer 10.2 Functional Description The Watchdog Timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, and a locking register. Once the Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written, which prevents the timer configuration from being inadvertently altered by software. The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt. After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down from that value. If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled (via the WatchdogResetEnable function), the Watchdog timer asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting resumes from that value. If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the counter is loaded with the new value and continues counting. Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared by writing to the Watchdog Interrupt Clear (WDTICR) register. The Watchdog module interrupt and reset generation can be enabled or disabled as required. When the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its last state. 10.3 Initialization and Configuration The Watchdog Timer is configured using the following sequence: 1. Load the WDTRLR register with the desired timer load value. 2. If the Watchdog will be configured to trigger system resets, set the RESEN bit in the WDTCTL register. 3. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register. If software requires that all of the watchdog registers are locked, the Watchdog Timer module can be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write a value of 0x1ACCE551. 10.4 Register Map Table 10-1 lists the Watchdog registers. All addresses given are relative to the Watchdog Timer base address of 0x40000000. Table 10-1. Offset 0x000 0x004 0x008 0x00C WDT Register Map Name WDTLOAD WDTVALUE WDTCTL WDTICR Reset 0xFFFFFFFF 0xFFFFFFFF 0x00000000 Type R/W RO R/W WO Description Load Current value Control Interrupt clear See page 163 164 165 166 161 Preliminary March 22, 2006 LM3S101 Data Sheet Table 10-1. Offset 0x010 0x014 0xC00 0xFD0 0xFD4 0xFD8 0xFDC 0xFE0 0xFE4 0xFE8 0xFEC 0xFF0 0xFF4 0xFF8 0xFFC WDT Register Map Name WDTRIS WDTMIS WDTLOCK WDTPeriphID4 WDTPeriphID5 WDTPeriphID6 WDTPeriphID7 WDTPeriphID0 WDTPeriphID1 WDTPeriphID2 WDTPeriphID3 WDTPCellID0 WDTPCellID1 WDTPCellID2 WDTPCellID0 Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000005 0x00000018 0x00000018 0x00000001 0x0000000D 0x000000F0 0x00000005 0x000000B1 Type RO RO R/W RO RO RO RO RO RO RO RO RO RO RO RO Description Raw interrupt status Masked interrupt status Lock Peripheral identification 4 Peripheral identification 5 Peripheral identification 6 Peripheral identification 7 Peripheral identification 0 Peripheral identification 1 Peripheral identification 2 Peripheral identification 3 PrimeCell identification 0 PrimeCell identification 1 PrimeCell identification 2 PrimeCell identification 3 See page 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 10.5 Register Descriptions The remainder of this section lists and describes the WDT registers, in numerical order by address offset. March 22, 2006 Preliminary 162 Watchdog Timer Register 1: Watchdog Load (WDTLOAD), offset 0x000 This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the value is immediately loaded and the counter restarts counting down from the new value. If the WDTLOAD register is loaded with 0x00000000, an interrupt is immediately generated. Watchdog Load (WDTLOAD) Offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTLoad Type Reset R/W 1 15 R/W 1 14 R/W 1 13 R/W 1 12 R/W 1 11 R/W 1 10 R/W 1 9 R/W 1 8 R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 WDTLoad Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field 31:0 Name WDTLoad Type R/W Reset 0xFFFFFFFF Description Watchdog Load Value 163 Preliminary March 22, 2006 LM3S101 Data Sheet Register 2: Watchdog Value (WDTVALUE), offset 0x004 This register contains the current count value of the timer. Watchdog Value (WDTVALUE) Offset 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTValue Type Reset RO 1 15 RO 1 14 RO 1 13 RO 1 12 RO 1 11 RO 1 10 RO 1 9 RO 1 8 RO 1 7 RO 1 6 RO 1 5 RO 1 4 RO 1 3 RO 1 2 RO 1 1 RO 1 0 WDTValue Type Reset RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 Bit/Field 31:0 Name WDTValue Type RO Reset 0xFFFFFFFF Description Watchdog Value Current value of the 32-bit down counter. March 22, 2006 Preliminary 164 Watchdog Timer Register 3: Watchdog Control (WDTCTL), offset 0x008 This register is the watchdog control register. The watchdog timer can be configured to generate a reset signal (upon second time-out) or an interrupt on time-out. When the watchdog interrupt has been enabled, all subsequent writes to the control register are ignored. The only mechanism that can re-enable writes is a hardware reset. Watchdog Control (WDTCTL) Offset 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RESEN R/W 0 INTEN R/W 0 Bit/Field 31:2 1 Name reserved RESEN Type RO R/W Reset 0 0x0 Description Reserved bits return an indeterminate value, and should never be changed. Watchdog Reset Enable 0: Disabled. 1: Enable the Watchdog module reset output. 0 INTEN R/W 0x0 Watchdog Interrupt Enable 0: Interrupt event disabled (once this bit is set, it can only be cleared by a hardware reset) 1: Interrupt event enabled. Once enabled, all writes are ignored. 165 Preliminary March 22, 2006 LM3S101 Data Sheet Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x000 This register is the interrupt clear register. A write of any value to this register clears the Watchdog interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is indeterminate. Watchdog Interrupt Clear (WDTICR) Offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WdogIntClr Type Reset WO 15 WO 14 WO 13 WO 12 WO 11 WO 10 WO 9 WO 8 WO 7 WO 6 WO 5 WO 4 WO 3 WO 2 WO 1 WO 0 WdogIntClr Type Reset WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO - Bit/Field 31:0 Name WDTIntClr Type WO Reset - Description Watchdog Interrupt Clear March 22, 2006 Preliminary 166 Watchdog Timer Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 This register is the raw interrupt status register. Watchdog interrupt events can be monitored via this register if the controller interrupt is masked. Watchdog Raw Interrupt Status (WDTRIS) Offset 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 WDTRIS RO 0 Bit/Field 31:1 0 Name reserved WDTRIS Type RO RO Reset 0 0x0 Description Reserved bits return an indeterminate value, and should never be changed. Watchdog Raw Interrupt Status Gives the raw interrupt state (prior to masking) of WDTINTR. 167 Preliminary March 22, 2006 LM3S101 Data Sheet Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 This register is the masked interrupt status register. The value of this register is the logical AND of the raw interrupt bit and the Watchdog interrupt enable bit. Watchdog Masked Interrupt Status (WDTMIS) Offset 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 WDTMIS RO 0 Bit/Field 31:1 0 Name reserved WDTMIS Type RO RO Reset 0 0x0 Description Reserved bits return an indeterminate value, and should never be changed. Watchdog Masked Interrupt Status Gives the masked interrupt state (after masking) of the WDTINTR interrupt. March 22, 2006 Preliminary 168 Watchdog Timer Register 7: Watchdog Lock (WDTLOCK), offset 0xC00 Writing 0x1ACCE551 to the WDTLOCK register enables write access to all other registers. Writing any other value to the WDTLOCK register re-enables the locked state for register writes to all the other registers. Reading the WDTLOCK register returns the lock status rather than the 32-bit value written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns 0x00000001 (when locked; otherwise, the returned value is 0x00000000 (unlocked)). Watchdog Lock (WDTLOCK) Offset 0xC00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTLock Type Reset R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 R/W 0 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 WDTLock Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:0 Name WDTLock Type R/W Reset 0x0000 Description Watchdog Lock A write of the value 0x1ACCE551 unlocks the watchdog registers for write access. A write of any other value reapplies the lock, preventing any register updates. A read of this register returns the following values: Locked: 0x00000001 Unlocked: 0x00000000 169 Preliminary March 22, 2006 LM3S101 Data Sheet Register 8: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 4 (WDTPeriphID4) Offset 0xFD0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PID4 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 7:0 Name reserved PID4 Type RO RO Reset 0 0x00 Description Reserved bits return an indeterminate value, and should never be changed. WDT Peripheral ID Register[7:0] March 22, 2006 Preliminary 170 Watchdog Timer Register 9: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 5 (WDTPeriphID5) Offset 0xFD4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PID5 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 7:0 Name reserved PID5 Type RO RO Reset 0 0x00 Description Reserved bits return an indeterminate value, and should never be changed. WDT Peripheral ID Register[15:8] 171 Preliminary March 22, 2006 LM3S101 Data Sheet Register 10: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 6 (WDTPeriphID6) Offset 0xFD8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PID6 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 7:0 Name reserved PID6 Type RO RO Reset 0 0x00 Description Reserved bits return an indeterminate value, and should never be changed. WDT Peripheral ID Register[23:16] March 22, 2006 Preliminary 172 Watchdog Timer Register 11: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 7 (WDTPeriphID7) Offset 0xFDC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PID7 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 7:0 Name reserved PID7 Type RO RO Reset 0 0x00 Description Reserved bits return an indeterminate value, and should never be changed. WDT Peripheral ID Register[31:24] 173 Preliminary March 22, 2006 LM3S101 Data Sheet Register 12: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 0 (WDTPeriphID0) Offset 0xFE0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PID0 RO 0 RO 1 RO 0 RO 1 Bit/Field 31:8 7:0 Name reserved PID0 Type RO RO Reset 0 0x05 Description Reserved bits return an indeterminate value, and should never be changed. Watchdog Peripheral ID Register[7:0] March 22, 2006 Preliminary 174 Watchdog Timer Register 13: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 1 (WDTPeriphID1) Offset 0xFE4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 PID1 RO 1 RO 0 RO 0 RO 0 Bit/Field 31:8 7:0 Name reserved PID1 Type RO RO Reset 0 0x18 Description Reserved bits return an indeterminate value, and should never be changed. Watchdog Peripheral ID Register[15:8] 175 Preliminary March 22, 2006 LM3S101 Data Sheet Register 14: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 2 (WDTPeriphID2) Offset 0xFE8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 PID2 RO 1 RO 0 RO 0 RO 0 Bit/Field 31:8 7:0 Name reserved PID2 Type RO RO Reset 0 0x18 Description Reserved bits return an indeterminate value, and should never be changed. Watchdog Peripheral ID Register[23:16] March 22, 2006 Preliminary 176 Watchdog Timer Register 15: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 3 (WDTPeriphID3) Offset 0xFEC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PID3 RO 0 RO 0 RO 0 RO 1 Bit/Field 31:8 7:0 Name reserved PID3 Type RO RO Reset 0 0x01 Description Reserved bits return an indeterminate value, and should never be changed. Watchdog Peripheral ID Register[31:24] 177 Preliminary March 22, 2006 LM3S101 Data Sheet Register 16: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Primecell Identification 0 (WDTPCellID0) Offset 0xFF0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 CID0 RO 1 RO 1 RO 0 RO 1 Bit/Field 31:8 7:0 Name reserved CID0 Type RO RO Reset 0 0x0D Description Reserved bits return an indeterminate value, and should never be changed. Watchdog PrimeCell ID Register[7:0] March 22, 2006 Preliminary 178 Watchdog Timer Register 17: Watchdog PrimeCell Identification 1(WDTPCellID1), offset 0xFF4 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Primecell Identification 1 (WDTPCellID1) Offset 0xFF4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1 CID1 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 7:0 Name reserved CID1 Type RO RO Reset 0 0xF0 Description Reserved bits return an indeterminate value, and should never be changed. Watchdog PrimeCell ID Register[15:8] 179 Preliminary March 22, 2006 LM3S101 Data Sheet Register 18: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Primecell Identification 2 (WDTPCellID2) Offset 0xFF8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 CID2 RO 0 RO 1 RO 0 RO 1 Bit/Field 31:8 7:0 Name reserved CID2 Type RO RO Reset 0 0x05 Description Reserved bits return an indeterminate value, and should never be changed. Watchdog PrimeCell ID Register[23:16] March 22, 2006 Preliminary 180 Watchdog Timer Register 19: Watchdog PrimeCell Identification 3 (WDTPCellID0), offset 0xFFC The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Primecell Identification 3 (WDTPCellID3) Offset 0xFFC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 1 CID3 RO 0 RO 0 RO 0 RO 1 Bit/Field 31:8 7:0 Name reserved CID3 Type RO RO Reset 0 0xB1 Description Reserved bits return an indeterminate value, and should never be changed. Watchdog PrimeCell ID Register[15:8] 181 Preliminary March 22, 2006 LM3S101 Data Sheet 11 Universal Asynchronous Receiver/Transmitter (UART) The Universal Asynchronous Receiver/Transmitter (UART) provides fully programmable, 16C550type serial interface characteristics. The LM3S101 controller is equipped with one UART module. The UART has the following features: Separate transmit and receive FIFOs Programmable FIFO length, including 1-byte deep operation providing conventional doublebuffered interface FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 Programmable baud-rate generator allowing rates up to 460.8 Kbps Standard asynchronous communication bits for start, stop and parity False start bit detection Line-break generation and detection Fully programmable serial interface characteristics: - 5, 6, 7, or 8 data bits - Even, odd, stick, or no-parity bit generation/detection - 1 or 2 stop bit generation March 22, 2006 Preliminary 182 Universal Asynchronous Receiver/Transmitter (UART) 11.1 System Clock Block Diagram UART Block Diagram Figure 11-1. Interrupt Interrupt Control UARTIFLS UARTIM UARTMIS TXFIFO 16x8 Prime Cell UARTPCellID0 UARTPCellID1 UARTPCellID2 UARTPCellID3 . . . Transmitter Baud Rate Generator UARTIBRD UARTFBRD UnTx UARTRIS UARTICR UARTDR Peripheral ID UARTPeriphID0 UARTPeriphID1 UARTPeriphID2 UARTPeriphID3 UART PeriphID4 UARTPeriphID5 UARTPeriphID6 UARTPeriphID7 Control / Status UARTRSR/ECR UARTFR UARTLCRH UARTCTL RXFIFO 16x8 Receiver UnRx . . . 11.2 Functional Description The Stellaris UART performs the functions of parallel-to-serial and serial-to-parallel conversions. It is similar in functionality to a 16C550 UART, but is not register compatible. The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control (UARTCTL) register (see page 199). Transmit and receive are both enabled out of reset. Before any control registers are programmed, the UART must be disabled by clearing the UARTEN bit in UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. 11.2.1 Transmit/Receive Logic The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. The control logic outputs the serial bit stream beginning with a start bit, and followed by the data bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control registers. See Figure 11-2 for details. 183 Preliminary March 22, 2006 LM3S101 Data Sheet The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also performed, and their status accompanies the data that is written to the receive FIFO. Figure 11-2. UART Character Frame UnTX 1 0 n Start LSB MSB 5-8 data bits 1-2 stop bits Parity bit if enabled 11.2.2 Baud-Rate Generation The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The number formed by these two values is used by the baud-rate generator to determine the bit period. Having a fractional baud-rate divider allows the UART to generate all the standard baud rates. The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register (see page 195) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor (UARTFBRD) register (see page 196). The baud-rate divisor has the following relationship to the system clock: BRD (Baud-Rate Divisor) = BRDI + BRDF = SysClk / (16 * Baud Rate) Where BRDI is the integer part of the BRD and BRDF is the fractional part, separated by a decimal place. The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 to account for rounding errors: UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5) The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred to as Baud16). This reference clock is divided by 16 to generate the transmit clock, and is used for error detection during receive operations. Along with the UART Line Control, High Byte (UARTLCRH) register (see page 197), the UARTIBRD and UARTFBRD registers form an internal 30-bit register. This internal register is only updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register for the changes to take effect. To update the baud-rate registers, there are four possible sequences: UARTIBRD write, UARTFBRD write, and UARTLCRH write UARTFBRD write, UARTIBRD write, and UARTLCRH write UARTIBRD write and UARTLCRH write UARTFBRD write and UARTLCRH write 11.2.3 Data Transmission Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra four bits per character for status information. For transmission, data is written into the transmit FIFO. If the UART is enabled, it causes a data frame to start transmitting with the parameters March 22, 2006 Preliminary 184 Universal Asynchronous Receiver/Transmitter (UART) indicated in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 193) is asserted as soon as data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits. The UART can indicate that it is busy even though the UART may no longer be enabled. When the receiver is idle (the U0Rx is continuously 1) and the data input goes Low (a start bit has been received), the receive counter begins running and data is sampled on the eighth cycle of Baud16 (described in "Transmit/Receive Logic" on page 183). The start bit is valid if U0Rx is still low on the eighth cycle of Baud16, otherwise a false start bit is detected and it is ignored. Start bit errors can be viewed in the UART Receive Status (UARTRSR) register (see page 191). If the start bit was valid, successive data bits are sampled on every 16th cycle of Baud16 (that is, one bit period later) according to the programmed length of the data characters. The parity bit is then checked if parity mode was enabled. Data length and parity are defined in the UARTLCRH register. Lastly, a valid stop bit is confirmed if U0Rx is High, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO, with any error bits associated with that word. 11.2.4 FIFO Operation The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed via the UART Data (UARTDR) register (see page 189). Read operations of the UARTDR register return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data in the transmit FIFO. Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are enabled by setting the FEN bit in UARTLCRH (page 197). FIFO status can be monitored via the UART Flag (UARTFR) register (see page 193) and the UART Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The UARTFR register contains empty and full flags (TXFE, TXFF, RXFE and RXFF bits) and the UARTRSR register shows overrun status via the OE bit. The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO Level Select (UARTIFLS) register (see page 200). Both FIFOs can be individually configured to trigger interrupts at different levels. Available configurations include 1/8, 1/4, 1/2, 3/4 and 7/8. Foe example, if the 1/4 option is selected for the receive FIFO, the UART generates a receive interrupt after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the 1/2 mark. 11.2.5 Interrupts The UART can generate interrupts when the following conditions are observed: Overrun Error Break Error Parity Error Framing Error Receive Timeout Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met) Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met) 185 Preliminary March 22, 2006 LM3S101 Data Sheet All of the interrupt events are ORed together before being sent to the interrupt controller, so the UART can only generate a single interrupt request to the controller at any given time. Software can service multiple interrupt events in a single interrupt service routine by reading the UART Masked Interrupt Status (UARTMIS) register (see page 204). The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt Mask (UARTIM) register (see page 201) by setting the corresponding IM bit to 1. If interrupts are not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS) register (see page 203). Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 205). 11.2.6 Loopback Operation The UART can be placed into an internal loopback mode for diagnostic or debug work. This is accomplished by setting the LBE bit in the UARTCTL register (see page 199). In loopback mode, data transmitted on U0Tx is received on the U0Rx input. 11.3 Initialization and Configuration This section discusses the steps that are required for using a UART module. For this example, the system clock is assumed to be 20 MHz and the desired UART configuration is: 115200 baud rate Data length of 8 bits One stop bit No parity FIFOs disabled No interrupts The first thing to consider when programming the UART is the baud-rate divisor (BRD), since the UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the equation described in "Baud-Rate Generation" on page 184, the BRD can be calculated: BRD = 20,000,000 / (16 * 115,200) = 10.8507 which means that the DIVINT field of the UARTIBRD register (see page 195) should be set to 10. The value to be loaded into the UARTFBRD register (see page 196) is calculated by the equation: UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54 With the BRD values in hand, the UART configuration is written to the module in the following order: 1. Disable the UART by clearing the UARTEN bit in the UARTCTL register. 2. Write the integer portion of the BRD to the UARTIBRD register. 3. Write the fractional portion of the BRD to the UARTFBRD register. 4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of 0x00000060). 5. Enable the UART by setting the UARTEN bit in the UARTCTL register. March 22, 2006 Preliminary 186 Universal Asynchronous Receiver/Transmitter (UART) 11.4 Register Map Table 11-1 lists the UART registers. All addresses given are relative to the UART's base address: UART0: 0x4000C000 Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 199) before any of the control registers are reprogrammed. When the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. Table 11-1. Offset 0x000 0x004 UART Register Map Name UARTDR UARTRSR UARTECR Reset 0x00000000 0x00000000 Type R/W R/W Description Data Receive Status (read) Error Clear (write) 0x00000090 0x00000000 0x00000000 0x00000000 0x00000300 0x00000012 0x00000000 0x0000000F 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000011 0x00000000 0x00000018 0x00000001 0x0000000D 0x000000F0 0x00000005 0x000000B1 RO R/W R/W R/W R/W R/W R/W RO RO W1C RO RO RO RO RO RO RO RO RO RO RO RO Flag Register (read only) Integer Baud-Rate Divisor Fractional Baud-Rate Divisor Line Control Register, High byte Control Register Interrupt FIFO Level Select Interrupt Mask Raw Interrupt Status Masked Interrupt Status Interrupt Clear Peripheral identification 4 Peripheral identification 5 Peripheral identification 6 Peripheral identification 7 Peripheral identification 0 Peripheral identification 1 Peripheral identification 2 Peripheral identification 3 PrimeCell identification 0 PrimeCell identification 1 PrimeCell identification 2 PrimeCell identification 3 193 195 196 197 199 200 201 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 See page 189 191 0x018 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x040 0x044 0xFD0 0xFD4 0xFD8 0xFDC 0xFE0 0xFE4 0xFE8 0xFEC 0xFF0 0xFF4 0xFF8 0xFFC UARTFR UARTIBRD UARTFBRD UARTLCRH UARTCTL UARTIFLS UARTIM UARTRIS UARTMIS UARTICR UARTPeriphID4 UARTPeriphID5 UARTPeriphID6 UARTPeriphID7 UARTPeriphID0 UARTPeriphID1 UARTPeriphID2 UARTPeriphID3 UARTPCellID0 UARTPCellID1 UARTPCellID2 UARTPCellID3 187 Preliminary March 22, 2006 LM3S101 Data Sheet 11.5 Register Descriptions The remainder of this section lists and describes the UART registers, in numerical order by address offset. March 22, 2006 Preliminary 188 Universal Asynchronous Receiver/Transmitter (UART) Register 1: UART Data (UARTDR), offset 0x000 This register is the data register (the interface to the FIFOs). When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs are disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO). A write to this register initiates a transmission from the UART. For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity and overrun) is pushed onto the 12-bit wide receive FIFO. If FIFOs are disabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data can be retrieved by reading this register. UART Data (UARTDR) Offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 OE RO 0 BE RO 0 PE RO 0 FE RO 0 R/W 0 R/W 0 R/W 0 DATA R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit 31:12 11 Name reserved OE Type RO RO Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. UART Overrun Error 1=New data was received when the FIFO was full, resulting in data loss. 0=There has been no data loss due to a FIFO overrun. 10 BE RO 0 UART Break Error This bit is set to 1 if a break condition was detected, indicating that the receive data input was held Low for longer than a fullword transmission time (defined as start, data, parity, and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. 9 PE RO 0 UART Parity Error This bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. In FIFO mode, this error is associated with the character at the top of the FIFO. 189 Preliminary March 22, 2006 LM3S101 Data Sheet Bit 8 Name FE Type RO Reset 0 Description UART Framing Error When this bit is set to 1, it indicates that the received character did not have a valid stop bit. (A valid stop bit is 1.) 7:0 DATA R/W 0 When written, the data that is to be transmitted via the UART. When read, the data that was received by the UART. March 22, 2006 Preliminary 190 Universal Asynchronous Receiver/Transmitter (UART) Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 The UARTRSR/UARTECR register is the receive status register/error clear register. In addition to the UARTDR register, receive status can also be read from the UARTRSR register. If the status is read from this register, then the status information corresponds to the entry read from UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when an overrun condition occurs. A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors. All the bits are cleared to 0 on reset. UART Receive Status (UARTRSR): Read Offset 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 OE RO 0 BE RO 0 PE RO 0 FE RO 0 UART Error Clear (UARTECR): Write Offset 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset WO 0 15 WO 0 14 WO 0 13 WO 0 12 WO 0 11 WO 0 10 WO 0 9 WO 0 8 WO 0 7 WO 0 6 WO 0 5 WO 0 4 WO 0 3 WO 0 2 WO 0 1 WO 0 0 reserved Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 DATA WO 0 WO 0 WO 0 WO 0 Bit Name Type Reset Description Read-Only Receive Status (UARTRSR) 31:4 3 reserved OE RO RO 0 0 Reserved bits return an indeterminate value, and should never be changed. The UARTRSR register cannot be written. UART Overrun Error When this bit is set to 1, data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid since no further data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data in order to empty the FIFO. This register cannot be written. 191 Preliminary March 22, 2006 LM3S101 Data Sheet Bit 2 Name BE Type RO Reset 0 Description UART Break Error This bit is set to 1 when a break condition is detected, indicating that the received data input was held Low for longer than a fullword transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. This register cannot be written. 1 PE RO 0 UART Parity Error This bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. This bit is cleared to 0 by a write to UARTECR. This register cannot be written. 0 FE RO 0 UART Framing Error This bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. This register cannot be written. Write-Only Error Clear (UARTECR) 31:8 7:0 reserved DATA WO WO 0 0 Reserved bits return an indeterminate value, and should never be changed. The UARTECR register cannot be read. A write to this register of any data clears the framing, parity, break and overrun flags. The UARTECR register cannot be read. March 22, 2006 Preliminary 192 Universal Asynchronous Receiver/Transmitter (UART) Register 3: UART Flag (UARTFR), offset 0x018 The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and TXFE and RXFE bits are 1. UART Flag (UARTFR) Offset 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 TXFE RO 1 RXFF RO 0 TXFF RO 0 RXFE RO 1 BUSY RO 0 RO 0 reserved RO 0 RO 0 Bit 31:8 7 Name reserved TXFE Type RO RO Reset 0 1 Description Reserved bits return an indeterminate value, and should never be changed. UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, this bit is set when the transmit FIFO is empty. 6 RXFF RO 0 UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, this bit is set when the receive FIFO is full. 5 TXFF RO 0 UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, this bit is set when the transmit FIFO is full. 193 Preliminary March 22, 2006 LM3S101 Data Sheet Bit 4 Name RXFE Type RO Reset 1 Description UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, this bit is set when the receive FIFO is empty. 3 BUSY RO 0 UART Busy When this bit is 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty (regardless of whether UART is enabled or not). 2:0 reserved RO 0 Reserved bits return an indeterminate value, and should never be changed. March 22, 2006 Preliminary 194 Universal Asynchronous Receiver/Transmitter (UART) Register 4: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD register is ignored. When changing the UARTIBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See "Baud-Rate Generation" on page 184 for configuration details. UART Integer Baud-Rate Divisor Offset 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 DIVINT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit 31:16 15:0 Name reserved DIVINT Type RO R/W Reset 0 0x00 Description Reserved bits return an indeterminate value, and should never be changed. Integer Baud-Rate Divisor 195 Preliminary March 22, 2006 LM3S101 Data Sheet Register 5: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared on reset. When changing the UARTFBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See "Baud-Rate Generation" on page 184 for configuration details. UART Fractional Baud-Rate Divisor (UARTFBRD) Offset 0x028 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 DIVFRAC R/W 0 R/W 0 R/W 0 R/W 0 Bit 31:6 5:0 Name reserved DIVFRAC Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. Fractional Baud-Rate Divisor March 22, 2006 Preliminary 196 Universal Asynchronous Receiver/Transmitter (UART) Register 6: UART Line Control (UARTLCRH), offset 0x02C The UARTLCRH register is the line control register. Serial parameters such as data length, parity and stop bit selection are implemented in this register. When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH register. UART Line Control (UARTLCRH) Offset 0x02C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 SPS R/W 0 WLEN R/W 0 R/W 0 FEN R/W 0 STP2 R/W 0 EPS R/W 0 PEN R/W 0 BRK R/W 0 Bit 31:8 7 Name reserved SPS Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. UART Stick Parity Select When bits 1, 2 and 7 of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the parity bit is transmitted and checked as a 1. When this bit is cleared, stick parity is disabled. 6:5 WLEN R/W 0 UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows: 0x3: 8 bits 0x2: 7 bits 0x1: 6 bits 0x0: 5 bits (default) 4 FEN R/W 0 UART Enable FIFOs If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO mode). When cleared to 0, FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers. 3 STP2 R/W 0 UART Two Stop Bits Select If this bit is set to 1, two stop bits are transmitted at the end of a frame. The receive logic does not check for two stop bits being received. 197 Preliminary March 22, 2006 LM3S101 Data Sheet Bit 2 Name EPS Type R/W Reset 0 Description UART Even Parity Select If this bit is set to 1, even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. When cleared to 0, then odd parity is performed, which checks for an odd number of 1s. This bit has no effect when parity is disabled by the PEN bit. 1 PEN R/W 0 UART Parity Enable If this bit is set to 1, parity checking and generation is enabled; otherwise, parity is disabled and no parity bit is added to the data frame. 0 BRK R/W 0 UART Send Break If this bit is set to 1, a Low level is continually output on the UnTX output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two frames (character periods). For normal use, this bit must be cleared to 0. March 22, 2006 Preliminary 198 Universal Asynchronous Receiver/Transmitter (UART) Register 7: UART Control (UARTCTL), offset 0x030 The UARTCTL register is the control register. All the bits are cleared on reset except for the Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1. To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration change in the module, the UARTEN bit must be cleared before the configuration changes are written. If the UART is disabled during a transmit or receive operation, the current transaction is completed prior to the UART stopping. UART Control (UARTCR) Offset 0x030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RXE R/W 1 TXE R/W 1 LBE R/W 0 RO 0 RO 0 RO 0 reserved RO 0 RO 0 RO 0 UARTEN R/W 0 Bit 31:10 9 Name reserved RXE Type RO R/W Reset 0 1 Description Reserved bits return an indeterminate value, and should never be changed. UART Receive Enable If this bit is set to 1, the receive section of the UART is enabled. When the UART is disabled in the middle of a receive, it completes the current character before stopping. 8 TXE R/W 1 UART Transmit Enable If this bit is set to 1, the transmit section of the UART is enabled. When the UART is disabled in the middle of a transmission, it completes the current character before stopping. 7 LBE R/W 0 UART Loop Back Enable If this bit is set to 1, the UnTX path is fed through the UnRX path. 6:1 0 reserved UARTEN RO R/W 0 0 Read as zero. UART Enable If this bit is set to 1, the UART is enabled. When the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 199 Preliminary March 22, 2006 LM3S101 Data Sheet Register 8: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define the FIFO level at which the TXRIS and RXRIS are triggered. The interrupts are generated based on a transition through a level rather than being based on the level. That is, the interrupts are generated when the fill level progresses through the trigger level. For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the module is receiving the 9th character. Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark. UART Interrupt FIFO Level Select (UARTIFLS) Offset 0x034 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 RXIFLSEL R/W 1 R/W 0 R/W 0 TXIFLSEL R/W 1 R/W 0 Bit 31:6 5:3 Name reserved RXIFLSEL Type RO R/W Reset 0 0X2 Description Reserved bits return an indeterminate value, and should never be changed. UART Receive Interrupt FIFO Level Select 000: RX FIFO 1/8 full 001: RX FIFO 1/4 full 010: RX FIFO 1/2 full (default) 011: RX FIFO 3/4 full 100: RX FIFO 7/8 full 101-111: Reserved 2:0 TXIFLSEL R/W 0X2 UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: 000: TX FIFO 1/8 full 001: TX FIFO 1/4 full 010: TX FIFO 1/2 full (default) 011: TX FIFO 3/4 full 100: TX FIFO 7/8 full 101-111: Reserved March 22, 2006 Preliminary 200 Universal Asynchronous Receiver/Transmitter (UART) Register 9: UART Interrupt Mask (UARTIM), offset 0x038 The UARTIM register is the interrupt mask set/clear register. On a read, this register gives the current value of the mask on the relevant interrupt. Writing a 1 to a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Writing a 0 prevents the raw interrupt signal from being sent to the interrupt controller. UART Interrupt Mask (UARTIM) Offset 0x038 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 OEIM R/W 0 BEIM R/W 0 PEIM R/W 0 FEIM R/W 0 RTIM R/W 0 TXIM R/W 0 RXIM R/W 0 RO 0 reserved RO 0 RO 0 RO 0 Bit 31:11 10 Name reserved OEIM Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. UART Overrun Error Interrupt Mask On a read, the current mask for the OEIM interrupt is returned. Setting this bit to 1 promotes the OEIM interrupt to the interrupt controller. 9 BEIM R/W 0 UART Break Error Interrupt Mask On a read, the current mask for the BEIM interrupt is returned. Setting this bit to 1 promotes the BEIM interrupt to the interrupt controller. 8 PEIM R/W 0 UART Parity Error Interrupt Mask On a read, the current mask for the PEIM interrupt is returned. Setting this bit to 1 promotes the PEIM interrupt to the interrupt controller. 7 FEIM R/W 0 UART Framing Error Interrupt Mask On a read, the current mask for the FEIM interrupt is returned. Setting this bit to 1 promotes the FEIM interrupt to the interrupt controller. 6 RTIM R/W 0 UART Receive Time-Out Interrupt Mask On a read, the current mask for the RTIM interrupt is returned. Setting this bit to 1 promotes the RTIM interrupt to the interrupt controller. 201 Preliminary March 22, 2006 LM3S101 Data Sheet Bit 5 Name TXIM Type R/W Reset 0 Description UART Transmit Interrupt Mask On a read, the current mask for the TXIM interrupt is returned. Setting this bit to 1 promotes the TXIM interrupt to the interrupt controller. 4 RXIM R/W 0 UART Receive Interrupt Mask On a read, the current mask for the RXIM interrupt is returned. Setting this bit to 1 promotes the RXIM interrupt to the interrupt controller. 3:0 reserved RO 0 Reserved bits return an indeterminate value, and should never be changed. March 22, 2006 Preliminary 202 Universal Asynchronous Receiver/Transmitter (UART) Register 10: UART Raw Interrupt Status (UARTRIS), offset 0x03C The UARTRIS register is the raw interrupt status register. On a read this register gives the current raw status value of the corresponding interrupt. A write has no effect. UART Raw Interrupt Status (UARTRIS) Offset 0x03C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 OERIS RO 0 BERIS RO 0 PERIS RO 0 FERIS RO 0 RTRIS RO 0 TXRIS RO 0 RXRIS RO 0 RO 1 RO 1 reserved RO 1 RO 1 Bit 31:11 10 Name reserved OERIS Type RO RO Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. UART Overrun Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 9 BERIS RO 0 UART Break Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 8 PERIS RO 0 UART Parity Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 7 FERIS RO 0 UART Framing Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 6 RTRIS RO 0 UART Receive Time-Out Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 5 TXRIS RO 0 UART Transmit Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 4 RXRIS RO 0 UART Receive Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 3:0 reserved RO 0xF This reserved bit is read-only. 203 Preliminary March 22, 2006 LM3S101 Data Sheet Register 11: UART Masked Interrupt Status (UARTMIS), offset 0x040 The UARTMIS register is the masked interrupt status register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. UART Masked Interrupt Status (UARTMIS) Offset 0x040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 OEMIS RO 0 BEMIS RO 0 PEMIS RO 0 FEMIS RO 0 RTMIS RO 0 TXMIS RXMIS RO 0 RO 0 RO 0 RO 0 reserved RO 0 RO 0 Bit 31:11 10 Name reserved OEMIS Type RO RO Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. UART Overrun Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 9 BEMIS RO 0 UART Break Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 8 PEMIS RO 0 UART Parity Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 7 FEMIS RO 0 UART Framing Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 6 RTMIS RO 0 UART Receive Time-Out Masked Interrupt Status Gives the masked interrupt state of this interrupt. 5 TXMIS RO 0 UART Transmit Masked Interrupt Status Gives the masked interrupt state of this interrupt. 4 RXMIS RO 0 UART Receive Masked Interrupt Status Gives the masked interrupt state of this interrupt. 3:0 reserved RO 0 Reserved bits return an indeterminate value, and should never be changed. March 22, 2006 Preliminary 204 Universal Asynchronous Receiver/Transmitter (UART) Register 12: UART Interrupt Clear (UARTICR), offset 0x044 The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect. UART Interrupt Clear (UARTICR) Offset 0x044 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 OEIC W1C 0 BEIC W1C 0 PEIC W1C 0 FEIC W1C 0 RTIC W1C 0 TXIC W1C 0 RXIC W1C 0 RO 0 RO 0 reserved RO 0 RO 0 Bit 31:11 10 Name reserved OEIC Type RO W1C Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. Overrun Error Interrupt Clear 0: No effect on the interrupt 1: Clears interrupt 9 BEIC W1C 0 Break Error Interrupt Clear 0: No effect on the interrupt 1: Clears interrupt 8 PEIC W1C 0 Parity Error Interrupt Clear 0: No effect on the interrupt 1: Clears interrupt 7 FEIC W1C 0 Framing Error Interrupt Clear 0: No effect on the interrupt 1: Clears interrupt 6 RTIC W1C 0 Receive Time-Out Interrupt Clear 0: No effect on the interrupt 1: Clears interrupt 5 TXIC W1C 0 Transmit Interrupt Clear 0: No effect on the interrupt 1: Clears interrupt 4 RXIC W1C 0 Receive Interrupt Clear 0: No effect on the interrupt 1: Clears interrupt 3:0 reserved RO 0 Reserved bits return an indeterminate value, and should never be changed. 205 Preliminary March 22, 2006 LM3S101 Data Sheet Register 13: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 4 (UARTPeriphID4) Offset 0xFD0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PID4 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 7:0 Name reserved PID4 Type RO RO Reset 0 0x0 Description Reserved bits return an indeterminate value, and should never be changed. UART Peripheral ID Register[7:0] March 22, 2006 Preliminary 206 Universal Asynchronous Receiver/Transmitter (UART) Register 14: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 5 (UARTPeriphID5) Offset 0xFD4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PID5 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 7:0 Name reserved PID5 Type RO RO Reset 0 0x0 Description Reserved bits return an indeterminate value, and should never be changed. UART Peripheral ID Register[15:8] 207 Preliminary March 22, 2006 LM3S101 Data Sheet Register 15: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 6 (UARTPeriphID6) Offset 0xFD8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PID6 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 7:0 Name reserved PID6 Type RO RO Reset 0 0x0 Description Reserved bits return an indeterminate value, and should never be changed. UART Peripheral ID Register[23:16] March 22, 2006 Preliminary 208 Universal Asynchronous Receiver/Transmitter (UART) Register 16: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 7 (UARTPeriphID7) Offset 0xFDC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PID7 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 7:0 Name reserved PID7 Type RO RO Reset 0 0x0 Description Reserved bits return an indeterminate value, and should never be changed. UART Peripheral ID Register[31:24] 209 Preliminary March 22, 2006 LM3S101 Data Sheet Register 17: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 0 (UARTPeriphID0) Offset 0xFE0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 PID0 RO 0 RO 0 RO 0 RO 1 Bit 31:8 7:0 Name reserved PID0 Type RO RO Reset 0 0x11 Description Reserved bits return an indeterminate value, and should never be changed. UART Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. March 22, 2006 Preliminary 210 Universal Asynchronous Receiver/Transmitter (UART) Register 18: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 1 (UARTPeriphID1) Offset 0xFE4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PID1 RO 0 RO 0 RO 0 RO 0 Bit 31:8 7:0 Name reserved PID1 Type RO RO Reset 0 0x0 Description Reserved bits return an indeterminate value, and should never be changed. UART Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 211 Preliminary March 22, 2006 LM3S101 Data Sheet Register 19: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 2 (UARTPeriphID2) Offset 0xFE8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 PID2 RO 1 RO 0 RO 0 RO 0 Bit 31:8 7:0 Name reserved PID2 Type RO RO Reset 0 0x18 Description Reserved bits return an indeterminate value, and should never be changed. UART Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. March 22, 2006 Preliminary 212 Universal Asynchronous Receiver/Transmitter (UART) Register 20: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 3 (UARTPeriphID3) Offset 0xFEC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PID3 RO 0 RO 0 RO 0 RO 1 Bit 31:8 7:0 Name reserved PID3 Type RO RO Reset 0 0x1 Description Reserved bits return an indeterminate value, and should never be changed. UART Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 213 Preliminary March 22, 2006 LM3S101 Data Sheet Register 21: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART Primecell Identification 0 (UARTPCellID0) Offset 0xFF0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 CID0 RO 1 RO 1 RO 0 RO 1 Bit 31:8 7:0 Name reserved CID0 Type RO RO Reset 0 0x0D Description Reserved bits return an indeterminate value, and should never be changed. UART PrimeCell ID Register[7:0] Provides software a standard cross-peripheral identification system. March 22, 2006 Preliminary 214 Universal Asynchronous Receiver/Transmitter (UART) Register 22: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART Primecell Identification 1 (UARTPCellID1) Offset 0xFF4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1 CID1 RO 0 RO 0 RO 0 RO 0 Bit 31:8 7:0 Name reserved CID1 Type RO RO Reset 0 0xF0 Description Reserved bits return an indeterminate value, and should never be changed. UART PrimeCell ID Register[15:8] Provides software a standard cross-peripheral identification system. 215 Preliminary March 22, 2006 LM3S101 Data Sheet Register 23: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART Primecell Identification 2 (UARTPCellID2) Offset 0xFF8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 CID2 RO 0 RO 1 RO 0 RO 1 Bit 31:8 7:0 Name reserved CID2 Type RO RO Reset 0 0x05 Description Reserved bits return an indeterminate value, and should never be changed. UART PrimeCell ID Register[23:16] Provides software a standard cross-peripheral identification system. March 22, 2006 Preliminary 216 Universal Asynchronous Receiver/Transmitter (UART) Register 24: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART Primecell Identification 3 (UARTPCellID3) Offset 0xFFC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 1 CID3 RO 0 RO 0 RO 0 RO 1 Bit 31:8 7:0 Name reserved CID3 Type RO RO Reset 0 0xB1 Description Reserved bits return an indeterminate value, and should never be changed. UART PrimeCell ID Register[31:24] Provides software a standard cross-peripheral identification system. 217 Preliminary March 22, 2006 LM3S101 Data Sheet 12 Synchronous Serial Interface (SSI) The Synchronous Serial Interface (SSI) is a master or slave interface for synchronous serial communication with peripheral devices that have either Freescale SPI, National Semiconductor MICROWIRE, or Texas Instruments synchronous serial interfaces. The Stellaris SSI has the following features: Master or slave operation Programmable clock bit rate and prescale Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep Programmable interface operation for Freescale SPI, National Semiconductor MICROWIRE, or Texas Instruments synchronous serial interfaces Programmable data frame size from 4 to 16 bits Internal loopback test mode for diagnostic/debug testing 12.1 Block Diagram SSI Block Diagram Interrupt Control SSIIM SSIMIS Control / Status SSICR0 SSICR1 SSISR SSIDR RxFIFO 8 x 16 Transmit/ Receive Logic SSIRIS SSIICR TxFIFO 8 x 16 Figure 12-1. Interrupt . . . SSITx SSIRx SSICLK SSIFss System Clock Clock Prescaler SSICPSR Peripheral ID SSIPeriphID0 Prime Cell SSIPCellID0 SSIPCellID1 SSIPCellID2 SSIPCellID3 . . . . . . SSIPeriphID7 March 22, 2006 Preliminary 218 Synchronous Serial Interface (SSI) 12.2 Functional Description The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU accesses data, control, and status information. The transmit and receive paths are buffered with internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. 12.2.1 Bit Rate Generation The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output clock. Bit rates are supported to 1.5 MHz and higher, although maximum bit rate is determined by peripheral devices. The serial bit rate is derived by dividing down the 20-MHz input clock. The clock is first divided by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale (SSICPSR) register (see page 234). The clock is further divided by a value from 1 to 256, which is 1 + SCR, where SCR is the value programmed in the SSI Control0 (SSICR0) register (see page 229). The frequency of the output clock SSIClk is defined by: FSSIClk = FSysClk / (CPSDVR * (1 + SCR)) Note that although the SSIClk transmit clock can theoretically be 10 MHz, the module may not be able to operate at that speed. For transmit operations, the system clock must be at least two times faster than the SSIClk. For receive operations, the system clock must be at least 12 times faster than the SSIClk. See "Electrical Characteristics" on page 271 to view SSI timing parameters. 12.2.2 12.2.2.1 FIFO Operation Transmit FIFO The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 232), and data is stored in the FIFO until it is read out by the transmission logic. When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial conversion and transmission to the attached slave or master, respectively, through the SSITx pin. 12.2.2.2 Receive FIFO The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. Received data from the serial interface is stored in the buffer until read out by the CPU, which accesses the read FIFO by reading the SSIDR register. When configured as a master or slave, serial data received through the SSIRx pin is registered prior to parallel loading into the attached slave or master receive FIFO, respectively. 12.2.3 Interrupts The SSI can generate interrupts when the following conditions are observed: Transmit FIFO service Receive FIFO service Receive FIFO time-out Receive FIFO overrun 219 Preliminary March 22, 2006 LM3S101 Data Sheet All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI can only generate a single interrupt request to the controller at any given time. You can mask each of the four individual maskable interrupts by setting the appropriate bits in the SSI Interrupt Mask (SSIIM) register (see page 235). Setting the appropriate mask bit to 1 enables the interrupt. Provision of the individual outputs, as well as a combined interrupt output, allows use of either a global interrupt service routine, or modular device drivers to handle interrupts. The transmit and receive dynamic dataflow interrupts have been separated from the status interrupts so that data can be read or written in response to the FIFO trigger levels. The status of the individual interrupt sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status (SSIMIS) registers (see page 236 and page 237, respectively). 12.2.4 Frame Formats Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is transmitted starting with the MSB. There are three basic frame types that can be selected: Texas Instruments synchronous serial Freescale SPI National Semiconductor MICROWIRE For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk transitions at the programmed frequency only during active transmission or reception of data. The idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive FIFO still contains data after a timeout period. For Freescale SPI and National Semiconductor MICROWIRE frame formats, the serial frame (SSIFss) pin is active Low, and is asserted (pulled down) during the entire transmission of the frame. For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial clock period starting at its rising edge, prior to the transmission of each frame. For this frame format, both the SSI and the off-chip slave device drive their output data on the rising edge of SSIClk, and latch data from the other device on the falling edge. Unlike the full-duplex transmission of the other two frame formats, the National Semiconductor MICROWIRE format uses a special master-slave messaging technique, which operates at halfduplex. In this mode, when a frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the requested data. The returned data can be 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. 12.2.4.1 Texas Instruments Synchronous Serial Frame Format Figure 12-2 shows the Texas Instruments synchronous serial frame format for a single transmitted frame. Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer) SSIClk SSIFss SSITx/SSIRx MSB 4 to 16 bits LSB March 22, 2006 Preliminary 220 Synchronous Serial Interface (SSI) In this mode, SSIClk and SSIFss are forced Low, and the transmit data line SSITx is tristated whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is pulsed High for one SSIClk period. The value to be transmitted is also transferred from the transmit FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIClk, the MSB of the 4 to 16-bit data frame is shifted out on the SSITx pin. Likewise, the MSB of the received data is shifted onto the SSIRx pin by the off-chip serial slave device. Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on the falling edge of each SSIClk. The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of SSIClk after the LSB has been latched. Figure 12-3 shows the Texas Instruments synchronous serial frame format when back-to-back frames are transmitted. Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer) SSIClk SSIFss SSITx/SSIRx MSB 4 to 16 bits LSB 12.2.4.2 Freescale SPI Frame Format The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave select. The main feature of the Freescale SPI format is that the inactive state and phase of the SSIClk signal are programmable through the SPO and SPH bits within the SSISCR0 control register. SPO Clock Polarity Bit When the SPO clock polarity control bit is Low, it produces a steady state Low value on the SSIClk pin. If the SPO bit is High, a steady state High value is placed on the SSIClk pin when data is not being transferred. SPH Phase Control Bit The SPH phase control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the SPH phase control bit is Low, data is captured on the first clock edge transition. If the SPH bit is High, data is captured on the second clock edge transition. 12.2.4.3 Freescale SPI Frame Format with SPO=0 and SPH=0 Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and SPH=0 are shown in Figure 12-4 and Figure 12-5. 221 Preliminary March 22, 2006 LM3S101 Data Sheet Figure 12-4. SSIClk SSIFss SSIRx Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 MSB 4 to 16 bits LSB Q SSITx MSB LSB Figure 12-5. SSIClk SSIFss Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 SSIRx LSB MSB 4 to 16 bits LSB MSB SSITx LSB MSB LSB MSB In this configuration, during idle periods: SSIClk is forced Low SSIFss is forced High The transmit data line SSITx is arbitrarily forced Low When the SSI is configured as a master, it enables the SSIClk pad When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. This causes slave data to be enabled onto the SSIRx input line of the master. The master SSITx output pad is enabled. One half SSIClk period later, valid master data is transferred to the SSITx pin. Now that both the master and slave data have been set, the SSIClk master clock pin goes High after one further half SSIClk period. The data is now captured on the rising and propagated on the falling edges of the SSIClk signal. In the case of a single word transmission, after all bits of the data word have been transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed High between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore, the master device must raise the SSIFss pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned to its idle state one SSIClk period after the last bit has been captured. 12.2.4.4 Freescale SPI Frame Format with SPO=0 and SPH=1 The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure 12-6, which covers both single and continuous transfers. March 22, 2006 Preliminary 222 Synchronous Serial Interface (SSI) Figure 12-6. SSIClk SSIFss SSIRx Q Freescale SPI Frame Format with SPO=0 and SPH=1 MSB 4 to 16 bits MSB LSB LSB Q SSITx In this configuration, during idle periods: SSIClk is forced Low SSIFss is forced High The transmit data line SSITx is arbitrarily forced Low When the SSI is configured as a master, it enables the SSIClk pad When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. The master SSITx output is enabled. After a further one half SSIClk period, both master and slave valid data is enabled onto their respective transmission lines. At the same time, the SSIClk is enabled with a rising edge transition. Data is then captured on the falling edges and propagated on the rising edges of the SSIClk signal. In the case of a single word transfer, after all bits have been transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words and termination is the same as that of the single word transfer. 12.2.4.5 Freescale SPI Frame Format with SPO=1 and SPH=0 Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and SPH=0 are shown in Figure 12-7 and Figure 12-8. Figure 12-7. SSIClk SSIFss SSIRx MSB 4 to 16 bits SSITx MSB LSB LSB Q Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 223 Preliminary March 22, 2006 LM3S101 Data Sheet Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 SSIClk SSIFss SSITx/SSIRx LSB MSB 4 to 16 bits LSB MSB In this configuration, during idle periods: SSIClk is forced High SSIFss is forced High The transmit data line SSITx is arbitrarily forced Low When the SSI is configured as a master, it enables the SSIClk pad When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low, which causes slave data to be immediately transferred onto the SSIRx line of the master. The master SSITx output pad is enabled. One half period later, valid master data is transferred to the SSITx line. Now that both the master and slave data have been set, the SSIClk master clock pin becomes Low after one further half SSIClk period. This means that data is captured on the falling edges and propagated on the rising edges of the SSIClk signal. In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed High between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore, the master device must raise the SSIFss pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned to its idle state one SSIClk period after the last bit has been captured. 12.2.4.6 Freescale SPI Frame Format with SPO=1 and SPH=1 The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure 12-9, which covers both single and continuous transfers. Figure 12-9. SSIClk SSIFss SSIRx Q MSB 4 to 16 bits SSITx MSB LSB LSB Q Freescale SPI Frame Format with SPO=1 and SPH=1 Note: Q is undefined in Figure 12-9. March 22, 2006 Preliminary 224 Synchronous Serial Interface (SSI) In this configuration, during idle periods: SSIClk is forced High SSIFss is forced High The transmit data line SSITx is arbitrarily forced Low When the SSI is configured as a master, it enables the SSIClk pad When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. The master SSITx output pad is enabled. After a further one-half SSIClk period, both master and slave data are enabled onto their respective transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then captured on the rising edges and propagated on the falling edges of the SSIClk signal. After all bits have been transferred, in the case of a single word transmission, the SSIFss line is returned to its idle high state one SSIClk period after the last bit has been captured. For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state, until the final bit of the last word has been captured, and then returns to its idle state as described above. For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words and termination is the same as that of the single word transfer. 12.2.4.7 National Semiconductor MICROWIRE Frame Format Figure 12-10 shows the National Semiconductor MICROWIRE frame format, again for a single frame. Figure 12-11 shows the same format when back-to-back frames are transmitted. Figure 12-10. National Semiconductor MICROWIRE Frame Format (Single Frame) SSIClk SSIFss SSITx SSIRx MSB LSB 8-bit control 0 MSB LSB 4 to 16 bits output data MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this transmission, no incoming data is received by the SSI. After the message has been sent, the offchip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. In this configuration, during idle periods: SSIClk is forced Low SSIFss is forced High The transmit data line SSITx is arbitrarily forced Low 225 Preliminary March 22, 2006 LM3S101 Data Sheet A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSIFss causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the SSITx pin. SSIFss remains Low for the duration of the frame transmission. The SSIRx pin remains tristated during this transmission. The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of each SSIClk. After the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven onto the SSIRx line on the falling edge of SSIClk. The SSI in turn latches each bit on the rising edge of SSIClk. At the end of the frame, for single transfers, the SSIFss signal is pulled High one clock period after the last bit has been latched in the receive serial shifter, which causes the data to be transferred to the receive FIFO. Note: The off-chip slave device can tristate the receive line either on the falling edge of SSIClk after the LSB has been latched by the receive shifter, or when the SSIFss pin goes High. For continuous transfers, data transmission begins and ends in the same manner as a single transfer. However, the SSIFss line is continuously asserted (held Low) and transmission of data occurs back-to-back. The control byte of the next frame follows directly after the LSB of the received data from the current frame. Each of the received values is transferred from the receive shifter on the falling edge of SSIClk, after the LSB of the frame has been latched into the SSI. Figure 12-11. National Semiconductor MICROWIRE Frame Format (Continuous Transfers) SSIClk SSIFss SSITx LSB MSB LSB 8-bit control SSIRx 0 MSB LSB MSB 4 to 16 bits output data In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk. Figure 12-12 illustrates these setup and hold time requirements. With respect to the SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss must have a setup of at least two times the period of SSIClk on which the SSI operates. With respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one SSIClk period. March 22, 2006 Preliminary 226 Synchronous Serial Interface (SSI) Figure 12-12. National Semiconductor MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements tSetup =(2*tSSIClk ) tHold=tSSIClk SSIClk SSIFss SSIRx First RX data to be sampled by SSI slave 12.3 Initialization and Configuration For each of the frame formats, the SSI is configured using the following steps: 1. Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration changes. 2. Select whether the SSI will be a master or slave: a. For master operations, set the SSICR1 register to 0x00000000. b. For slave mode (output enabled), set the SSICR1 register to 0x00000004. c. For slave mode (output disabled), set the SSICR1 register to 0x0000000C. 3. Configure the clock prescale divisor by writing the SSICPSR register. 4. Write the SSICR0 register with the following configuration: a. Serial clock rate (SCR) b. Desired clock phase/polarity, if using Freescale SPI mode (SPH/SPO) c. The protocol mode: Freescale SPI, TI SSF, National Semiconductor MICROWIRE (FRF) d. The data size (DSS) 5. Enable the SSI by setting the SSE bit in the SSICR1 register. As an example, assume the SSI must be configured to operate with the following parameters: Master operation Freescale SPI mode (SPO=1, SPH=1) 1 Mbps bit rate 8 data bits Assuming the system clock is 20 MHz, the bit rate calculation would be: FSSIClk = FSysClk / (CPSDVR * (1 + SCR)) ' 1x106 = 20x106 / (CPSDVR * (1 + SCR)) In this case, if CPSDVR=2, SCR must be 9. The configuration sequence would be as follows: 1. Ensure that the SSE bit in the SSICR1 register is disabled. 2. Write the SSICR1 register with a value of 0x00000000. 3. Write the SSICPSR register with a value of 0x00000002. 227 Preliminary March 22, 2006 LM3S101 Data Sheet 4. Write the SSICR0 register with a value of 0x000009C7. 5. The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1. 12.4 Register Map Table 12-1 lists the SSI registers. All addresses given are relative to the SSI base address of 0x40008000. Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control registers are reprogrammed. Table 12-1. Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0xFD0 0xFD4 0xFD8 0xFDC 0xFE0 0xFE4 0xFE8 0xFEC 0xFF0 0xFF4 0xFF8 0xFFC SSI Register Map Name SSICR0 SSICR1 SSIDR SSISR SSICPSR SSIIM SSIRIS SSIMIS SSIICR SSIPeriphID4 SSIPeriphID5 SSIPeriphID6 SSIPeriphID7 SSIPeriphID0 SSIPeriphID1 SSIPeriphID2 SSIPeriphID3 SSIPCellID0 SSIPCellID1 SSIPCellID2 SSIPCellID3 Reset 0x00000000 0x00000000 0x00000000 0x00000003 0x00000000 0x00000000 0x00000008 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000022 0x00000000 0x00000018 0x00000001 0x0000000D 0x000000F0 0x00000005 0x000000B1 Type RW RW RW RO RW RW RO RO W1C RO RO RO RO RO RO RO RO RO RO RO RO Description Control 0 Control 1 Data Status Clock prescale Interrupt mask Raw interrupt status Masked interrupt status Interrupt clear Peripheral identification 4 Peripheral identification 5 Peripheral identification 6 Peripheral identification 7 Peripheral identification 0 Peripheral identification 1 Peripheral identification 2 Peripheral identification 3 PrimeCell identification 0 PrimeCell identification 1 PrimeCell identification 2 PrimeCell identification 3 See page 229 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 12.5 Register Descriptions The remainder of this section lists and describes the SSI registers, in numerical order by address offset. March 22, 2006 Preliminary 228 Synchronous Serial Interface (SSI) Register 1: SSI Control 0 (SSICR0), offset 0x000 SSICR0 is control register 0 and contains bit fields that control various functions within the SSI module. Functionality such as protocol mode, clock rate and data size are configured in this register. SSI Control 0 (SSICR0) Offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 SCR Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 SPH R/W 0 SPO R/W 0 R/W 0 FRF R/W 0 R/W 0 R/W 0 DSS R/W 0 R/W 0 Bit 31:16 15:8 Name reserved SCR Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. SSI Serial Clock Rate The value SCR is used to generate the transmit and receive bit rate of the SSI. The bit rate is: BR= FSSICLK/(CPSDVR * (1 + SCR)) where CPSDVR is an even value from 2-254 programmed in the SSICPSR register, and SCR is a value from 0-255. 7 SPH R/W 0 SSI Serial Clock Phase This bit is only applicable to the Freescale SPI Format. The SPH control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the SPH bit is 0, data is captured on the first clock edge transition. If SPH is 1, data is captured on the second clock edge transition. 6 SPO R/W 0 SSI Serial Clock Polarity This bit is only applicable to the Freescale SPI Format. When the SPO bit is 0, it produces a steady state Low value on SSIClk pin. If SPO is 1, a steady state High value is placed on the SSIClk pin when data is not being transferred. 229 Preliminary March 22, 2006 LM3S101 Data Sheet Bit 5:4 Name FRF Type R/W Reset 0 Description SSI Frame Format Select. The FRF values are defined as follows: FRF Value 00 01 Frame Format Freescale SPI Frame Format Texas Instruments Synchronous Serial Frame Format National Semiconductor MICROWIRE Frame Format 10 3:0 DSS R/W 0 SSI Data Size Select The DSS values are defined as follows: DSS Value 0000-0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Data Size Reserved 4-bit data 5-bit data 6-bit data 7-bit data 8-bit data 9-bit data 10-bit data 11-bit data 12-bit data 13-bit data 14-bit data 15-bit data 16-bit data March 22, 2006 Preliminary 230 Synchronous Serial Interface (SSI) Register 2: SSI Control 1 (SSICR1), offset 0x004 SSICR1 is control register 1 and contains bit fields that control various functions within the SSI module. Master and slave mode functionality is controlled by this register. SSI Control 1 (SSCR1) Offset 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 SOD R/W 0 MS R/W 0 SSE R/W 0 LBM R/W 0 Bit/Field 31:4 3 Name reserved SOD Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. SSI Slave Mode Output Disable This bit is relevant only in the Slave mode (MS=1). In multipleslave systems, it is possible for the SSI master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto the serial output line. In such systems, the TXD lines from multiple slaves could be tied together. To operate in such a system, the SOD bit can be configured so that the SSI slave will not drive the SSITx pin. 0: SSI can drive SSITx output in Slave Output mode. 1: SSI must not drive the SSITx output in Slave mode. 2 MS R/W 0 SSI Master/Slave Select This bit selects Master or Slave mode and can be modified only when SSI is disabled (SSE=0). 0: Device configured as a master. 1: Device configured as a slave. 1 SSE R/W 0 SSI Synchronous Serial Port Enable Setting this bit enables SSI operation. Note: This bit must be set to 0 before any control registers are reprogrammed. 0: SSI operation disabled. 1: SSI operation enabled. 0 LBM R/W 0 SSI Loopback Mode Setting this bit enables Loopback Test mode. 0: Normal serial port operation enabled. 1: Output of the transmit serial shift register is connected internally to the input of the receive serial shift register. 231 Preliminary March 22, 2006 LM3S101 Data Sheet Register 3: SSI Data (SSIDR), offset 0x008 SSIDR is the data register and is 16-bits wide. When SSIDR is read, the entry in the receive FIFO (pointed to by the current FIFO read pointer) is accessed. As data values are removed by the SSI receive logic from the incoming data frame, they are placed into the entry in the receive FIFO (pointed to by the current FIFO write pointer). When SSIDR is written to, the entry in the transmit FIFO (pointed to by the write pointer), is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSITx pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. When the SSI is programmed for National Semiconductor MICROWIRE frame format, the default size for transmit data is eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer. The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1 register is set to zero. This allows the software to fill the transmit FIFO before enabling the SSI. SSI Data (SSIDR) Offset 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 DATA Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:16 15:0 Name reserved DATA Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. SSI Receive/Transmit Data A read operation reads the receive FIFO. A write operation writes the transmit FIFO. Software must right-justify data when the SSI is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by the transmit logic. The receive logic automatically right-justifies the data. March 22, 2006 Preliminary 232 Synchronous Serial Interface (SSI) Register 4: SSI Status (SSISR), offset 0x00C SSISR is a status register that contains bits that indicate the FIFO fill status and the SSI busy status. SSI Status (SSISR) Offset 0x00C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 BSY RO 0 RFF RO 0 RNE RO 0 TNF RO 1 TFE RO 1 Bit/Field 31:5 4 Name reserved BSY Type RO RO Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. SSI Busy Bit 0: SSI is idle. 1: SSI is currently transmitting and/or receiving a frame, or the transmit FIFO is not empty. 3 RFF RO 0 SSI Receive FIFO Full 0: Receive FIFO is not full. 1: Receive FIFO is full. 2 RNE RO 0 SSI Receive FIFO Not Empty 0: Receive FIFO is empty. 1: Receive FIFO is not empty. 1 TNF RO 1 SSI Transmit FIFO Not Full 0: Transmit FIFO is full. 1: Transmit FIFO is not full. 0 TFE R0 1 SSI Transmit FIFO Empty 0: Transmit FIFO is not empty. 1: Transmit FIFO is empty. 233 Preliminary March 22, 2006 LM3S101 Data Sheet Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 SSICPSR is the clock prescale register and specifies the division factor by which the system clock must be internally divided before further use. The value programmed into this register must be an even number between 2 and 254. The leastsignificant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least-significant bit as zero. SSI Clock Prescale (SSICPSR) Offset 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 CPSDVSR R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:8 7:0 Name reserved CPSDVSR Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. SSI Clock Prescale Divisor This value must be an even number from 2 to 254, depending on the frequency of SSIClk. The LSB always returns 0 on reads. March 22, 2006 Preliminary 234 Synchronous Serial Interface (SSI) Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits are cleared to 0 on reset. On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. SSI Interrupt Mask (SSIIM) Offset 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 TXIM R/W 0 RXIM R/W 0 RTIM R/W 0 RORIM R/W 0 Bit/Field 31:4 3 Name reserved TXIM Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. SSI Transmit FIFO Interrupt Mask 0: TX FIFO half-empty or less condition interrupt is masked. 1: TX FIFO half-empty or less condition interrupt is not masked. 2 RXIM R/W 0 SSI Receive FIFO Interrupt Mask 0: RX FIFO half-full or less condition interrupt is masked. 1: RX FIFO half-full or less condition interrupt is not masked. 1 RTIM R/W 0 SSI Receive Time-Out Interrupt Mask 0: RX FIFO time-out interrupt is masked. 1: RX FIFO time-out interrupt is not masked. 0 RORIM R/W 0 SSI Receive Overrun Interrupt Mask 0: RX FIFO overrun interrupt is masked. 1: RX FIFO overrun interrupt is not masked. 235 Preliminary March 22, 2006 LM3S101 Data Sheet Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 The SSIRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. SSI Raw Interrupt Status (SSIRIS) Offset 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 TXRIS RO 1 RXRIS RO 0 RTRIS RORRIS RO 0 RO 0 Bit/Field 31:4 3 Name reserved TXRIS Type RO RO Reset 0 1 Description Reserved bits return an indeterminate value, and should never be changed. SSI Transmit FIFO Raw Interrupt Status Indicates that the transmit FIFO is half empty or more, when set. 2 RXRIS RO 0 SSI Receive FIFO Raw Interrupt Status Indicates that the receive FIFO is half empty or more, when set. 1 RTRIS RO 0 SSI Receive Time-Out Raw Interrupt Status Indicates that the receive time-out has occurred, when set. 0 RORRIS RO 0 SSI Receive Overrun Raw Interrupt Status Indicates that the receive FIFO has overflowed, when set. March 22, 2006 Preliminary 236 Synchronous Serial Interface (SSI) Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C The SSIMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. SSI Masked Interrupt Status (SSIMIS) Offset 0x01C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 TXMIS RXMIS RO 0 RO 0 RTMIS RORMIS RO 0 RO 0 Bit/Field 31:4 3 Name reserved TXMIS Type RO RO Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. SSI Transmit FIFO Masked Interrupt Status Indicates that the transmit FIFO is half empty or more, when set. 2 RXMIS RO 0 SSI Receive FIFO Masked Interrupt Status Indicates that the receive FIFO is half empty or more, when set. 1 RTMIS RO 0 SSI Receive Time-Out Masked Interrupt Status Indicates that the receive time-out has occurred, when set. 0 RORMIS RO 0 SSI Receive Overrun Masked Interrupt Status Indicates that the receive FIFO has overflowed, when set. 237 Preliminary March 22, 2006 LM3S101 Data Sheet Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 The SSIPICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. SSI Interrupt Clear (SSIICR) Offset 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RTIC W1C 0 RORIC W1C 0 Bit/Field 31:2 1 Name reserved RTIC Type RO W1C Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. SSI Receive Time-Out Interrupt Clear 0: No effect on interrupt. 1: Clears interrupt. 0 RORIC W1C 0 SSI Receive Overrun Interrupt Clear 0: No effect on interrupt. 1: Clears interrupt. March 22, 2006 Preliminary 238 Synchronous Serial Interface (SSI) Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 4 (SSIPeriphID4) Offset 0xFD0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PID4 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 7:0 Name reserved PID4 Type RO RO Reset 0 0x00 Description Reserved bits return an indeterminate value, and should never be changed. SSI Peripheral ID Register[7:0] 239 Preliminary March 22, 2006 LM3S101 Data Sheet Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 5 (SSIPeriphID5) Offset 0xFD4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PID5 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 7:0 Name reserved PID5 Type RO RO Reset 0 0x00 Description Reserved bits return an indeterminate value, and should never be changed. SSI Peripheral ID Register[15:8] March 22, 2006 Preliminary 240 Synchronous Serial Interface (SSI) Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 6 (SSIPeriphID6) Offset 0xFD8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PID6 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 7:0 Name reserved PID6 Type RO RO Reset 0 0x00 Description Reserved bits return an indeterminate value, and should never be changed. SSI Peripheral ID Register[23:16] 241 Preliminary March 22, 2006 LM3S101 Data Sheet Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 7 (SSIPeriphID7) Offset 0xFDC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PID7 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 7:0 Name reserved PID7 Type RO RO Reset 0 0x00 Description Reserved bits return an indeterminate value, and should never be changed. SSI Peripheral ID Register[31:24] March 22, 2006 Preliminary 242 Synchronous Serial Interface (SSI) Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 0 (SSIPeriphID0) Offset 0xFEO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 PID0 RO 0 RO 0 RO 1 RO 0 Bit/Field 31:8 7:0 Name reserved PID0 Type RO RO Reset 0 0x22 Description Reserved bits return an indeterminate value, and should never be changed. SSI Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 243 Preliminary March 22, 2006 LM3S101 Data Sheet Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 1 (SSIPeriphID1) Offset 0xFE4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PID1 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 7:0 Name reserved PID1 Type RO RO Reset 0 0x0 Description Reserved bits return an indeterminate value, and should never be changed. SSI Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. March 22, 2006 Preliminary 244 Synchronous Serial Interface (SSI) Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 2 (SSIPeriphID2) Offset 0xFE8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 PID2 RO 1 RO 0 RO 0 RO 0 Bit/Field 31:8 7:0 Name reserved PID2 Type RO RO Reset 0 0x18 Description Reserved bits return an indeterminate value, and should never be changed. SSI Peripheral ID Register [23:16] Can be used by software to identify the presence of this peripheral. 245 Preliminary March 22, 2006 LM3S101 Data Sheet Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 3 (SSIPeriphID3) Offset 0xFEC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PID3 RO 0 RO 0 RO 0 RO 1 Bit/Field 31:8 7:0 Name reserved PID3 Type RO RO Reset 0 0x1 Description Reserved bits return an indeterminate value, and should never be changed. SSI Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. March 22, 2006 Preliminary 246 Synchronous Serial Interface (SSI) Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset value. SSI Primecell Identification 0 (SSIPCellID0) Offset 0xFF0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 CID0 RO 1 RO 1 RO 0 RO 1 Bit/Field 31:8 7:0 Name reserved CID0 Type RO RO Reset 0 0x0D Description Reserved bits return an indeterminate value, and should never be changed. SSI PrimeCell ID Register [7:0] Provides software a standard cross-peripheral identification system. 247 Preliminary March 22, 2006 LM3S101 Data Sheet Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset value. SSI Primecell Identification 1 (SSIPCellID1) Offset 0xFF4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1 CID1 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 7:0 Name reserved CID1 Type RO RO Reset 0 0xF0 Description Reserved bits return an indeterminate value, and should never be changed. SSI PrimeCell ID Register [15:8] Provides software a standard cross-peripheral identification system. March 22, 2006 Preliminary 248 Synchronous Serial Interface (SSI) Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset value. SSI Primecell Identification 2 (SSIPCellID2) Offset 0xFF8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 CID2 RO 0 RO 1 RO 0 RO 1 Bit/Field 31:8 7:0 Name reserved CID2 Type RO RO Reset 0 0x05 Description Reserved bits return an indeterminate value, and should never be changed. SSI PrimeCell ID Register [23:16] Provides software a standard cross-peripheral identification system. 249 Preliminary March 22, 2006 LM3S101 Data Sheet Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset value. SSI Primecell Identification 3 (SSIPCellID3) Offset 0xFFC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 1 CID3 RO 0 RO 0 RO 0 RO 1 Bit/Field 31:8 7:0 Name reserved CID3 Type RO RO Reset 0 0xB1 Description Reserved bits return an indeterminate value, and should never be changed. SSI PrimeCell ID Register [31:24] Provides software a standard cross-peripheral identification system. March 22, 2006 Preliminary 250 Analog Comparators 13 Analog Comparators An analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result. The LM3S101 controller provides two independent integrated analog comparators that can be configured to drive an output or generate an interrupt. A comparator can compare a test voltage against any one of these voltages: An individual external reference voltage A shared single external reference voltage A shared internal reference voltage The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts to cause it to start capturing a sample sequence. The interrupt generation logic is separate. 13.1 Block Diagram Figure 13-1. Analog Comparator Block Diagram C1 Comparator 0 output C0o Voltage Ref internal bus ACREFCTL 13.2 Functional Description Important: If a comparator input is configured as an analog input that is not a full scale value (0 V or 3.3 V only), the input Schmitt Trigger is required to be disabled via the GPIO module. The comparator compares the VIN- and VIN+ inputs to produce an output, VOUT. As shown in Figure 13-2, the input source for VIN- is an external input. In addition to an external input, input sources for VIN+ can be the +ve input of comparator 0 or an internal reference. 251 Preliminary March 22, 2006 LM3S101 Data Sheet Figure 13-2. Structure of Comparator Unit -ve input +ve input 0 output CINV IntGen +ve input (alternate) 1 reference input 2 ACCTL ACSTAT internal bus A comparator is configured through two status/control registers (ACCTL and ACSTAT). The internal reference is configured through one control register (ACREFCTL). Interrupt status and control is configured through three registers (ACMIS, ACRIS, and ACINTEN). The operating modes of the comparators are shown in Table 13-1 and Table 13-2. Typically, the comparator output is used internally to generate controller interrupts. It may also be used to drive an external pin. Note: The proper pad configuration for the comparator input and output pins are described in Table 8-1 on page 97. Comparator 0 Operating Modes Comparator 0 VINC0C0C0C0VIN+ C0+ C0+ Vref reserved Output C0o/C1C0o/C1C0o/C1C0o/C1Interrupt yes yes yes yes Table 13-1. ACCNTL0 ASRCP 00 01 10 11 Table 13-2. Comparator 1 Operating Modes Comparator 1 VINC0o/C1-a C0o/C1C0o/C1C0o/C1VIN+ n/a C0+ Vref reserved Output n/a n/a n/a n/a Interrupt yes yes yes yes ACCNTL1 ASRCP 00 01 10 11 a. C0o and C1- signals share a single pin and may only be used as one or the other. March 22, 2006 Preliminary interrupt 252 Analog Comparators 13.2.1 Internal Reference Programming The structure of the internal reference is shown in Figure 13-3. This is controlled by a single configuration register (ACREFCTL). Table 13-3 shows the programming options to develop specific internal reference values, to compare an external voltage against a particular voltage generated internally. Figure 13-3. Comparator Internal Reference Structure AVDD 8R R R *** EN 15 VREF RNG 14 *** Decoder 1 0 internal reference R R 8R Table 13-3. Internal Reference Voltage and ACREFCTL Field Values Output Reference Voltage Based on VREF Field Value ACREFCTL Register EN Bit Value EN=0 EN=1 RNG Bit Value RNG=X RNG=0 0 V (GND) for any value of VREF; however, it is recommended that RNG=1 and VREF=0 for the least noisy ground reference. Total resistance in ladder is 32 R. R VREF V REF = AV DD x --------------RT ( VREF + 8 ) VREF = AVDD x ----------------------------32 VREF = 0.825 + 0.103 VREF The range of internal reference in this mode is 0.825-2.37 V. RNG=1 Total resistance in ladder is 24 R. R VREF V REF = AV DD x --------------RT ( VREF ) V REF = AV DD x ------------------24 V REF = 0.1375 VREF The range of internal reference for this mode is 0.0-2.0625 V. 253 Preliminary March 22, 2006 LM3S101 Data Sheet 13.3 Register Map Table 13-4 lists the comparator registers. All addresses given are relative to the Analog Comparator base address of 0x4003C000. Table 13-4. Offset 0x00 0X04 0X08 0x10 0x20 0x40 0x24 0x44 Analog Comparator Register Map Name ACMIS ACRIS ACINTEN ACREFCTL ACSTAT0 ACSTAT1 ACCTL0 ACCTL1 Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Type RO RO R/W R/W RO RO RW RW Description Interrupt status Raw interrupt status Interrupt enable Reference voltage control Comparator 0 status Comparator 1 status Comparator 0 control Comparator 1 control See page 255 256 257 258 259 259 260 260 13.4 Register Descriptions The remainder of this section lists and describes the Analog Comparator registers, in numerical order by address offset. March 22, 2006 Preliminary 254 Analog Comparators Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 This register provides a summary of the interrupt status (masked) of the comparators. Analog Comparator Masked Interrupt Status (ACMIS) Offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 IN1 RO 0 IN0 RO 0 Bit/Field 31:2 1 Name reserved IN1 Type RO RO Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. Comparator 1 Masked Interrupt Status Gives the masked interrupt state of this interrupt. 0 IN0 RO 0 Comparator 0 Masked Interrupt Status Gives the masked interrupt state of this interrupt. 255 Preliminary March 22, 2006 LM3S101 Data Sheet Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 This register provides a summary of the interrupt status (raw) of the comparators. Analog Comparator Raw Interrupt Status (ACRIS) Offset 0x04 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 IN1 RO 0 IN0 RO 0 Bit/Field 31:2 1 0 Name reserved IN1 IN0 Type RO RO RO Reset 0 0 0 Description Reserved bits return an indeterminate value, and should never be changed. When set, indicates that an interrupt has been generated by comparator 1. When set, indicates that an interrupt has been generated by comparator 0. March 22, 2006 Preliminary 256 Analog Comparators Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 This register provides the interrupt enable for the comparators. Analog Comparator Interrupt Enable (ACINTEN) Offset 0x08 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 IN1 R/W RO 0 IN0 R/W RO 0 Bit/Field 31:2 1 0 Name reserved IN1 IN0 Type RO R/W R/W Reset 0 0 0 Description Reserved bits return an indeterminate value, and should never be changed. When set, enables the controller interrupt from the comparator 1 output. When set, enables the controller interrupt from the comparator 0 output. 257 Preliminary March 22, 2006 LM3S101 Data Sheet Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 This register specifies whether the resistor ladder is powered on as well as the range and tap. Analog Comparator Reference Voltage Control (ACREFCTL) Offset 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved EN RNG Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W RO 0 R/W RO 0 RO 0 RO 0 RO 0 RO 0 R/W RO 0 R/W RO 0 VREF R/W RO 0 R/W RO 0 Bit/Field 31:10 9 Name reserved EN Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. The EN bit specifies whether the resistor ladder is powered on. If 0, the resistor ladder is unpowered. If 1, the resistor ladder is connected to the analog VDD. This bit is reset to 0 so that the internal reference consumes the least amount of power if not used and programmed. 8 RNG R/W 0 The RNG bit specifies the range of the resistor ladder. If 0, the resistor ladder has a total resistance of 32 R. If 1, the resistor ladder has a total resistance of 24 R. Reserved bits return an indeterminate value, and should never be changed. The VREF bit field specifies the resistor ladder tap that is passed through an analog multiplexer. The voltage corresponding to the tap position is the internal reference voltage available for comparison. 7:4 3:0 reserved VREF RO R/W 0 0 March 22, 2006 Preliminary 258 Analog Comparators Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40 These registers specify the current output value of that comparator. Analog Comparator Status 0 (ACSTAT0) Offset 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 OVAL RO 0 reserved RO 0 Bit/Field 31:2 1 0 Name reserved OVAL reserved Type RO RO RO Reset 0 0 0 Description Reserved bits return an indeterminate value, and should never be changed. The OVAL bit specifies the current output value of the comparator. Reserved bits return an indeterminate value, and should never be changed. 259 Preliminary March 22, 2006 LM3S101 Data Sheet Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x24 Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x44 These registers configure that comparator's input and output. Analog Comparator Control 0 (ACCTL0) Offset 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 ASRCP R/W RO 0 R/W RO 0 RO 0 reserved RO 0 RO 0 RO 0 ISLVAL R/W RO 0 R/W RO 0 ISEN R/W RO 0 CINV R/W RO 0 reserved RO RO 0 Bit/Field 31:11 10:9 Name reserved ASRCP Type RO R/W Reset 0 0 Description Reserved bits return an indeterminate value, and should never be changed. The ASRCP field specifies the source of input voltage to the VIN+ terminal of the comparator. The encodings for this field are as follows: ASRCP 00 01 10 11 Function Pin value Pin value of C0+ Internal voltage reference Reserved 8:5 4 reserved ISLVAL RO R/W 0 0 Reserved bits return an indeterminate value, and should never be changed. The ISLVAL bit specifies the sense value of the input that generates an interrupt if in Level Sense mode. If 0, an interrupt is generated if the comparator output is Low. Otherwise, an interrupt is generated if the comparator output is High. March 22, 2006 Preliminary 260 Analog Comparators Bit/Field 3:2 Name ISEN Type R/W Reset 0 Description The ISEN field specifies the sense of the comparator output that generates an interrupt. The sense conditioning is as follows: ISEN 00 01 10 11 Function Level sense, see ISLVAL Falling edge Rising edge Either edge 1 CINV R/W 0 The CINV bit conditionally inverts the output of the comparator. If 0, the output of the comparator is unchanged. If 1, the output of the comparator is inverted prior to being processed by hardware. Reserved bits return an indeterminate value, and should never be changed. 0 reserved RO 0 261 Preliminary March 22, 2006 LM3S101 Data Sheet 14 Pin Diagram Figure 14-1 shows the pin diagram and pin-to-signal-name mapping. Figure 14-1. Pin Connection Diagram PB7/TRST PB6/C0+ PB5/C0o/C1PB4/C0RST LDO VDD GND OSC0 OSC1 PA0/U0Rx PA1/U0Tx PA2/SSIClk PA3/SSIFss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PC0/TCK/SWCLK PC1/TMS/SWDIO PC2/TDI PC3/TDO/SWO PB3 PB2 VDD GND PB1/32KHz PB0/CCP0 GND VDD PA5/SSITx PA4/SSIRx LM3S101 March 22, 2006 Preliminary 262 Signal Tables 15 Signal Tables The following tables list the signals available for each pin. Functionality is enabled by software with the GPIOAFSEL register (see page 109). Important: All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins (PB7 and PC[3:0]) which default to the JTAG functionality. Table 15-1 shows the pin-to-signal-name mapping, including functional characteristics of the signals. Table 15-2 lists the signals in alphabetical order by signal name. Table 15-3 groups the signals by functionality. Table 15-4 lists the GPIO pins and their alternate functionality. Table 15-1. Pin Number 1 Signals by Pin Number (Sheet 1 of 2) Signal Name PB7 TRST Pin Type I/O I I/O I I/O O I I/O I I I O I/O I I/O O I/O I/O Buffer Type TTL TTL TTL Analog TTL TTL Analog TTL Analog TTL Power Power Power Analog Analog TTL TTL TTL TTL TTL TTL Description GPIO port B bit 7. JTAG TAP reset input. GPIO port B bit 6. Analog comparator 0 positive reference input. GPIO port B bit 5. Analog comparator 0 output. Analog comparator 1 negative reference input. GPIO port B bit 4. Analog comparator 0 negative reference input. System reset input. The linear drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 F or greater. Positive supply for logic and I/O pins. Ground reference for logic and I/O pins. Oscillator crystal input or an external clock reference input. Oscillator crystal output. GPIO port A bit 0. UART0 receive data input. GPIO port A bit 1. UART0 transmit data output. GPIO port A bit 2. SSI clock reference (input when in slave mode and output in master mode). 2 PB6 C0+ 3 PB5 C0o C1- 4 PB4 C0- 5 6 7 8 9 10 11 RST LDO VDD GND OSC0 OSC1 PA0 U0Rx 12 PA1 U0Tx 13 PA2 SSIClk 263 Preliminary March 22, 2006 LM3S101 Data Sheet Table 15-1. Pin Number 14 Signals by Pin Number (Sheet 2 of 2) Signal Name PA3 SSIFss Pin Type I/O I/O I/O I I/O O I/O I/O I/O I I/O I/O I/O O O I/O I I/O I I/O I/O I I Buffer Type TTL TTL TTL TTL TTL TTL Power Power TTL TTL TTL TTL Power Power TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL Description GPIO port A bit 3. SSI frame enable (input for an SSI slave device and output for an SSI master device). GPIO port A bit 4. SSI receive data input. GPIO port A bit 5. SSI transmit data output. Positive supply for logic and I/O pins. Ground reference for logic and I/O pins. GPIO port B bit 0. Timer 0 capture input, compare output, or PWM output port 0. GPIO port B bit 1. Timer clock reference input for real-time clock operation. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. GPIO port B bit 2. GPIO port B bit 3. GPIO port C bit 3. JTAG scan test output. Serial-wire output. GPIO port C bit 2. JTAG scan data input. GPIO port C bit 1. JTAG mode select input. Serial-wire debug input/output. GPIO port C bit 0. JTAG scan clock reference input. Serial-wire clock reference input. 15 PA4 SSIRx 16 PA5 SSITx 17 18 19 VDD GND PB0 CCP0 20 PB1 32KHz 21 22 23 24 25 GND VDD PB2 PB3 PC3 TDO SWO 26 PC2 TDI 27 PC1 TMS SWDIO 28 PC0 TCK SWCLK March 22, 2006 Preliminary 264 Signal Tables Table 15-2. Signal Name 32KHz C0+ C0- C0o C1- CCP0 GND GND GND LDO OSC0 OSC1 PA0 PA1 PA2 PA3 PA4 PA5 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 Signals by Signal Name (Sheet 1 of 2) Pin Number 20 2 4 3 3 19 8 18 21 6 9 10 11 12 13 14 15 16 19 20 23 24 4 3 2 1 28 27 Pin Type I I I O I I/O I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Buffer Type TTL Analog Analog TTL Analog TTL Power Power Power Power Analog Analog TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL Description Timer clock reference input for real-time clock operation. Analog comparator 0 positive reference input. Analog comparator 0 negative reference input. Analog comparator 0 output. Analog comparator 1 negative reference input. Timer 0 capture input, compare output, or PWM output port 0. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. The linear drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 F or greater. Oscillator crystal input or an external clock reference input. Oscillator crystal output. GPIO port A bit 0. GPIO port A bit 1. GPIO port A bit 2. GPIO port A bit 3. GPIO port A bit 4. GPIO port A bit 5. GPIO port B bit 0. GPIO port B bit 1. GPIO port B bit 2. GPIO port B bit 3. GPIO port B bit 4. GPIO port B bit 5. GPIO port B bit 6. GPIO port B bit 7. GPIO port C bit 0. GPIO port C bit 1. 265 Preliminary March 22, 2006 LM3S101 Data Sheet Table 15-2. Signal Name PC2 PC3 RST SSIClk SSIFss SSIRx SSITx SWCLK SWDIO SWO TCK TDI TDO TMS TRST U0Rx U0Tx VDD VDD VDD Signals by Signal Name (Sheet 2 of 2) Pin Number 26 25 5 13 14 15 16 28 27 25 28 26 25 27 1 11 12 7 17 22 Pin Type I/O I/O I I/O I/O I O I I/O O I I O I I I O Buffer Type TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL Power Power Power Description GPIO port C bit 2. GPIO port C bit 3. System reset input. SSI clock reference (input when in slave mode and output in master mode). SSI frame enable (input for an SSI slave device and output for an SSI master device). SSI receive data input. SSI transmit data output. Serial-wire clock reference input. Serial-wire debug input/output. Serial-wire output. JTAG scan clock reference input. JTAG scan data input. JTAG scan test output. JTAG mode select input. JTAG TAP reset input. UART0 receive data input. UART0 transmit data output. Positive supply for logic and I/O pins. Positive supply for logic and I/O pins. Positive supply for logic and I/O pins. March 22, 2006 Preliminary 266 Signal Tables Table 15-3. Function Analog Comparator Signals by Function, Except for GPIO (Sheet 1 of 2) Signal Name C0+ C0- C0o C1- Pin Number 2 4 3 3 20 19 28 27 25 28 26 25 27 1 8 18 21 6 Pin Type I I O I I I/O I I/O O I I O I I Buffer Type Analog Analog TTL Analog TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL Power Power Power Power Description Analog comparator 0 positive reference input. Analog comparator 0 negative reference input. Analog comparator 0 output. Analog comparator 1 negative reference input. Timer clock reference input for real-time clock operation. Timer 0 capture input, compare output, or PWM output port 0. Serial wire clock reference input. Serial-wire debug input/output. Serial-wire output. JTAG scan clock reference input. JTAG scan data input. JTAG scan test output. JTAG mode select input. JTAG TAP reset input. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. The linear drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 F or greater. Positive supply for logic and I/O pins. Positive supply for logic and I/O pins. Positive supply for logic and I/O pins. General-Purpose Timers 32KHz CCP0 JTAG/SWD/SWO SWCLK SWDIO SWO TCK TDI TDO TMS TRST Power GND GND GND LDO VDD VDD VDD 7 17 22 - Power Power Power 267 Preliminary March 22, 2006 LM3S101 Data Sheet Table 15-3. Function SSI Signals by Function, Except for GPIO (Sheet 2 of 2) Signal Name SSIClk SSIFss SSIRx SSITx Pin Number 13 14 15 16 9 10 5 11 12 Pin Type I/O I/O I O I O I I O Buffer Type TTL TTL TTL TTL Analog Analog TTL TTL TTL Description SSI clock reference (input when in slave mode and output in master mode). SSI frame enable (input for an SSI slave device and output for an SSI master device). SSI receive data input. SSI transmit data output. Oscillator crystal input or an external clock reference input. Oscillator crystal output. System reset input. UART0 receive data input. UART0 transmit data output. System Control & Clocks OSC0 OSC1 RST UART U0Rx U0Tx Table 15-4. GPIO Pin PA0 PA1 PA2 PA3 PA4 PA5 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 GPIO Pins and Alternate Functions (Sheet 1 of 2) Pin Number 11 12 13 14 15 16 19 20 23 24 4 3 2 1 28 C0C0o C0+ TRST TCK SWCLK C1Multiplexed Function U0Rx U0Tx SSIClk SSIFss SSIRx SSITx CCP0 32KHz Multiplexed Function March 22, 2006 Preliminary 268 Signal Tables Table 15-4. GPIO Pin PC1 PC2 PC3 GPIO Pins and Alternate Functions (Sheet 2 of 2) Pin Number 27 26 25 Multiplexed Function TMS TDI TDO SWO Multiplexed Function SWDIO 269 Preliminary March 22, 2006 LM3S101 Data Sheet 16 Table 16-1. Operating Characteristics Temperature Characteristics Symbol TA Value 0 to +70 for commercial -40 to +85 for industrial Unit C Characteristic Operating temperature rangea a. Maximum storage temperature is 150C. Table 16-2. Characteristic Thermal Characteristics Symbol JA TJ TJMAX Value 74 TA + (PAVG * JA) TBD Unit C/W C C Thermal resistance (junction to ambient)a Average junction temperatureb Maximum junction temperature a. Junction to ambient thermal resistance JA numbers are determined by a package simulator. b. Power dissipation is a function of temperature. March 22, 2006 Preliminary 270 Electrical Characteristics 17 17.1 17.1.1 Electrical Characteristics DC Characteristics Maximum Ratings The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note: The device is not guaranteed to operate properly at the maximum ratings. Maximum Ratings Symbol VDD VIN I I Value 0 to +3.6 -0.3 to 5.5 100 100 Unit V V mA mA Table 17-1. Characteristica Supply voltage range (VDD) Input voltage Maximum current for pins, excluding pins operating as GPIOs Maximum current for GPIO pins a. Voltages are measured with respect to GND. Important: This device contains circuitry to protect the inputs against damage due to high-static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this highimpedance circuit. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either VSS or VDD). 17.1.2 Recommended DC Operating Conditions Table 17-2. Parameter VDD VSS VIH VIL VSIH VSIL VOH VOL Recommended DC Operating Conditions Parameter Name Supply voltage Supply ground High-level input voltage Low-level input voltage High-level input voltage for Schottky inputs Low-level input voltage for Schottky inputs High-level output voltage Low-level output voltage TBD 3.3 0 Min 3 0 2 -.3 TBD TBD TBD Nom 3.3 0 Max 3.6 0 5 1.3 Unit V V V V V V V V 271 Preliminary March 22, 2006 LM3S101 Data Sheet Table 17-2. Parameter IOHa Recommended DC Operating Conditions Parameter Name Low-level source current, VOH=TBD Min Nom Max Unit mA IOL High-level source current, VOH=TBD mA a. Different GPIO drive strengths. 17.1.3 On-Chip Linear Drop-Out (LDO) Regulator Characteristics Table 17-3. Parameter VLDOOUT LDO Regulator Characteristics Parameter Name Programmable internal (logic) power supply output value Output voltage accuracy Min 0.9 2% 100 200 100 50 1 s s s mV F Nom Max 3.3 Unit V tPON tON tOFF VSTEP CLDO Power-on time Time on Time off Step programming incremental voltage External filter capacitor size for internal power supply 17.1.4 Power Specifications VDD=3.3 V LDO=2.5 Temperature=25 C System Clock=20 MHz (with PLL) Table 17-4. Parameter IDDrun Power Specifications Parameter Name Run mode Min Nom TBD Max Unit mA March 22, 2006 Preliminary 272 Electrical Characteristics Table 17-4. Parameter IDDsleep IDDdeepsleep Power Specifications Parameter Name Sleep mode Deep-sleep mode Min Nom TBD TBD Max Unit A A 17.1.5 Power-Up and Low-Voltage (Brown-Out) Detect Characteristics Table 17-5. Parameter VTHa tPOR VBTH tBOR Power-Up and Brown-Out Detect Characteristics Parameter Name Power-up threshold voltage Power-up assertion time Brown-out threshold voltage Brown-out assertion time 500 Min Nom 2 10 3 Max Unit V ms V s a. The internal power-on reset circuit may be used unless the power supply slew rate (SRPS) is less than the following relation. If so, the brown-out detector triggers immediately after the internal reset is released: SRPS < (VBTH-VTH)/ tPOR 17.1.6 Flash Memory Characteristics Table 17-6. Parameter PEcyc Tret Tprog Terase Tme Flash Memory Characteristics Parameter Name Maximum number of guaranteed program/ erase cyclesa before failure Data retention at average operating temperature of 85C Word program time Page erase time Mass erase time Min 10,000 10 20 20 200 Nom Max Unit cycles years s ms ms a. A program/erase cycle is defined as switching the bits from 1-> 0 -> 1. 17.2 17.2.1 AC Characteristics Load Conditions TBD 273 Preliminary March 22, 2006 LM3S101 Data Sheet 17.2.2 Clocks Table 17-7. Parameter fref_crystal fref_ext fref_crystal_bypas s Phase Locked Loop (PLL) Characteristics Parameter Name Crystal referencea External referencea PLL bypass PLL bypassb PLL frequencyb PLL lock time Min 3.579545 3.579545 1 0 200 0.5 Nom Max 8.192 8.192 8 20 Unit MHz MHz MHz MHz MHz ms fref_ext_bypass fpll TREADY a. The exact value is determined by the crystal value programmed into the XTAL field of the Run-Mode Clock Configuration (RCC) register (see page 70). b. PLL frequency is automatically calculated by the hardware based on the XTAL field of the RCC register. Table 17-8. Parameter fBOSC fMOSC tMOSC_per fsystem_clock Clock Characteristics Parameter Name Boot oscillator frequency Main oscillator frequency Main oscillator period System clock Min 10.5 1 1000 0 Nom 15 Max 19.5 8 125 20 Unit MHz MHz ms MHz 17.2.3 Analog Comparator TBD March 22, 2006 Preliminary 274 Electrical Characteristics 17.2.4 Table 17-9. Parameter No. S1 S2 S3 S4 S5 S6 S7 S8 S9 Synchronous Serial Interface (SSI) SSI Characteristics Parameter tclk_per tclk_high tclk_low tclkrf tDMd tDMs tDMh tDSs tDSh Parameter Name SSIClk cycle time SSIClk high time SSIClk low time SSIClk rise/fall time Data from master valid delay time Data from master setup time Data from master hold time Data from slave setup time Data from slave hold time Min TBD TBD TBD TBD TBD Nom tSSIClk (tSSIClk)/2 (tSSIClk)/2 Max TBD TBD Unit ns ns ns ns ns ns ns ns ns Figure 17-1. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement S1 S2 S4 SSIClk S3 SSIFss SSITx SSIRx MSB 4 to 16 bits LSB 275 Preliminary March 22, 2006 LM3S101 Data Sheet Figure 17-2. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer S2 S1 SSIClk S3 SSIFss SSITx MSB 8-bit control LSB SSIRx 0 MSB 4 to 16 bits output data LSB Figure 17-3. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 S1 S4 S2 SSIClk (SPO=0) S3 SSIClk (SPO=1) S6 S7 SSITx (master) S5 MSB S8 S9 LSB LSB SSIRx (slave) SSIFss MSB March 22, 2006 Preliminary 276 Electrical Characteristics 17.2.5 JTAG and Boundary Scan JTAG Characteristics Parameter fJCYC tJCYC tJCW tJCR tJCF tBSDST tBSDHT tBSDV tBSDZ tTAPBST tTAPBHT tTDODV tTDODZ tTRSTAT tTRSTST Parameter Name TCLK Frequency of operation TCLK Cycle Period TCLK Pulse Width TCLK Rise time TCLK Fall time TDI input data setup time to TCLK Rise TDI input data hold time (after TCLK rise) TCLK Low to Boundary Scan Output Data Valid TCLK Low to Boundary Scan Output High Z TMS, TDI Input Data Setup Time to TCLK Rise TMS, TDI Input Data Hold Time after TCLK Rise TCLK Low to TDO Valid TCLK Low to TDO High Z TRST Assert Time TRST Setup Time (Negation) to TCLK High Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Nom Max TBD TBD TBD TBD TBD TBD TBD Unit fsystem clock tCYC ns ns ns ns ns ns ns ns ns ns ns ns ns Table 17-10. Parameter No. J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 Figure 17-4. JTAG Test Clock Input Timing J2 J3 J3 TCLK J5 J4 277 Preliminary March 22, 2006 LM3S101 Data Sheet Figure 17-5. JTAG Boundary Scan Timing TCLK J6 J7 Data Inputs J8 Input Data Valid Output Data Valid J9 Data Outputs Data Outputs J8 Data Outputs Figure 17-6. JTAG Test Access Port (TAP) Timing Output Data Valid TCLK J10 J11 TDI TMS J12 Input Data Valid Output Data Valid J13 TDO TDO J12 TDO Figure 17-7. JTAG TRST Timing Output Data Valid TCLK J14 J15 /TRST March 22, 2006 Preliminary 278 Electrical Characteristics 17.2.6 General-Purpose I/O GPIO Characteristics Parameter Name GPO Rise Time (output) Condition 2 mA Drive 4 mA Drive 8 mA Drive 8 mA Drive with slew rate control OD 2 mA Drivea OD 4 mA Drivea OD 8 mA Drivea OD 8 mA Drive with slew rate controla Min Nom Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Table 17-11. Parameter tGPIOR tGPIOF GPO Fall Time (output) 2 mA Drive 4 mA Drive 8 mA Drive 8 mA Drive with slew rate control OD 2 mA Drive a OD 4 mA Drivea OD 8 mA Drivea OD 8 mA Drive with slew rate controla a. With external 2.8K pull-up resistor. When GPO is in Open Drain (OD) mode, internal pull-up and pull-down resistors are disabled. 17.2.7 Reset The specifications apply over the full operating temperature range: -55C to +125C. Typical values are at ambiant temperature TA=25C. Test conditions: VIN=3.3 V. Table 17-12. Parameter No. R1 R2 R3 R4 R5 R6 Reset Characteristics Parameter VTH VBTH TPOR TBOR TIRPOR TIRBOR Parameter Name Reset Threshold Brown-Out Threshold Power-On Reset Timeout Brown-Out Timeout Internal Reset Timeout After POR Internal Reset Timeout After BORa Min 15 2.5 10 500 Nom 2.0 Max 3.0 30 20 Unit V V ms s ms s 279 Preliminary March 22, 2006 LM3S101 Data Sheet Table 17-12. Parameter No. R7 R8 R9 R10 a. 20 * tMOSC_per Reset Characteristics Parameter TIRHWR TIRSWR TIRWDR TIRLDOR Parameter Name Internal Reset Timeout After Hardware Reset (RST pin) Internal Reset Timeout After Software Initiated System Reseta Internal Reset Timeout After Watchdog Reseta Internal Reset Timeout After LDO Reseta Min 15 2.5 2.5 2.5 Nom Max 30 20 20 20 Unit ms s s s Figure 17-8. External Reset Timing (RST) /RST R7 /Reset (Internal) Figure 17-9. Power-On Reset Timing R1 VDD R3 /POR (Internal) R5 /Reset (Internal) Figure 17-10. Brown-Out Reset Timing R2 VDD R4 /BOR (Internal) R6 /Reset (Internal) March 22, 2006 Preliminary 280 Electrical Characteristics Figure 17-11. Software Reset Timing SW Reset R8 /Reset (Internal) Figure 17-12. Watchdog Reset Timing WDT Reset (Internal) /Reset (Internal) Figure 17-13. LDO Reset Timing R9 LDO Reset (Internal) R10 /Reset (Internal) 281 Preliminary March 22, 2006 LM3S101 Data Sheet 18 Package Information 28-Pin SOIC Figure 18-1. March 22, 2006 Preliminary 282 Contact Information Ordering Information Features Speed (Clock Frequency in MHz) Shipping Mediumh T C 8 2 2 to 18 2 1 2 1 I RN 20 Xn P R P T R P PWM (CCP Pins)c Qualificationg Operating Temperatured UART SSI LM3S101-CRN20-XnPT LM3S101-CRN20-XnPR LM3S101-CRN20-XnPP LM3S101-IRN20-XnPT LM3S101-IRN20-XnPR LM3S101-IRN20-XnPP a. b. c. d. e. f. g. h. Minimum is number of pins dedicated to GPIO; additional pins are available if certain peripherals are not used. See data sheet for details. One timer available as RTC. PWM motion control functionality can be achieved through the motion control features of the general-purpose timers (using the CCP pins). See data sheet for details. C=Commercial (0 to 70C); I=Industrial (-40 to 85C). RN=28-pin RoHS-compliant SOIC. Xn=Part number will contain die revision number at order time, for example, B4. P=Production. T=Tray; R=Rail/Tube; P=Tape and Reel. Development Kit The Luminary Micro StellarisTM Family Development Kit provides the hardware and software tools that engineers need to begin development quickly. Ask your Luminary Micro distributor for part number DK-LM3S101. I2C Part Number Die Revisionf Analog Comparators SRAM (KB) Flash (KB) Packagee Timersb GPIOsa Tools to begin development quickly 283 Preliminary March 22, 2006 LM3S101 Data Sheet Company Information Luminary Micro, Inc. designs, markets, and sells ARM Cortex-M3 based microcontrollers for use in embedded applications within the industrial, commercial, and consumer markets. Luminary Micro is ARM's lead partner in the implementation of the Cortex-M3 core. Please contact us if you are interested in obtaining further information about our company or our products. Luminary Micro, Inc. 2499 South Capital of Texas Hwy, Suite A-100 Austin, TX 78746 Main: +1-512-279-8800 Fax: +1-512-279-8879 http://www.luminarymicro.com sales@luminarymicro.com Support Information For support on Luminary Micro products, contact: support@luminarymicro.com +1-512-279-8800, ext. 3 March 22, 2006 Preliminary 284 |
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